forked from Imagelibrary/rtems
9964895866
Adjust build support files to new directory layout. This patch is a part of the BSP source reorganization. Update #3285.
115 lines
2.2 KiB
ArmAsm
115 lines
2.2 KiB
ArmAsm
/**
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* @file
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*
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* @ingroup mpc55xx_asm
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*
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* @brief Cache initialization.
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*/
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/*
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* Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Obere Lagerstr. 30
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <libcpu/powerpc-utility.h>
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#include <mpc55xx/regs.h>
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.globl mpc55xx_start_cache
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.section ".bsp_start_text", "ax"
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mpc55xx_start_cache:
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#ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT
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/* Load zero, CINV, and CABT) */
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li r0, 0
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li r3, 0x2
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li r4, 0x4
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#if defined(BSP_INSTRUCTION_CACHE_ENABLED) \
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&& defined(MPC55XX_HAS_INSTRUCTION_CACHE)
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start_instruction_cache_invalidation:
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/* Clear instruction cache invalidation abort */
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mtspr FSL_EIS_L1CSR1, r0
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/* Start instruction cache invalidation */
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mtspr FSL_EIS_L1CSR1, r3
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get_instruction_cache_invalidation_status:
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/* Get instruction cache invalidation status */
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mfspr r5, FSL_EIS_L1CSR1
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/* Check CABT */
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and. r6, r5, r4
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bne start_instruction_cache_invalidation
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/* Check CINV */
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and. r6, r5, r3
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bne get_instruction_cache_invalidation_status
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/* Save instruction cache settings */
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LWI r6, 0x00010001
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isync
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msync
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mtspr FSL_EIS_L1CSR1, r6
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#endif
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#if (defined(BSP_DATA_CACHE_ENABLED) && defined(MPC55XX_HAS_DATA_CACHE)) \
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|| ((defined(BSP_DATA_CACHE_ENABLED) \
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|| defined(BSP_INSTRUCTION_CACHE_ENABLED)) \
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&& defined(MPC55XX_HAS_UNIFIED_CACHE))
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start_data_cache_invalidation:
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/* Clear data cache invalidation abort */
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mtspr FSL_EIS_L1CSR0, r0
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/* Start data cache invalidation */
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mtspr FSL_EIS_L1CSR0, r3
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get_data_cache_invalidation_status:
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/* Get data cache invalidation status */
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mfspr r5, FSL_EIS_L1CSR0
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/* Check CABT */
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and. r6, r5, r4
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bne start_data_cache_invalidation
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/* Check CINV */
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and. r6, r5, r3
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bne get_data_cache_invalidation_status
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/* Save data cache settings */
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#if MPC55XX_CHIP_FAMILY != 567
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/* FIXME: CORG??? 0x00180011 */
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LWI r6, 0x00100001
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#else
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LWI r6, 0x00190001
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#endif
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isync
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msync
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mtspr FSL_EIS_L1CSR0, r6
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#endif
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#endif /* MPC55XX_NEEDS_LOW_LEVEL_INIT */
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/* Return */
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blr
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