forked from Imagelibrary/rtems
238 lines
6.3 KiB
ArmAsm
238 lines
6.3 KiB
ArmAsm
/* dlentry.s
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*
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* This file contains the entry code for RTEMS programs starting
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* after download to RAM
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*
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* Author: Thomas Doerfler <td@imd.m.isar.de>
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* IMD Ingenieurbuero fuer Microcomputertechnik
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*
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* COPYRIGHT (c) 1998 by IMD
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*
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* Changes from IMD are covered by the original distributions terms.
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* This file has been derived from the papyrus BSP:
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*
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* This file contains the entry veneer for RTEMS programs
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* downloaded to Papyrus.
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*
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* Author: Andrew Bray <andy@i-cubed.co.uk>
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*
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* COPYRIGHT (c) 1995 by i-cubed ltd.
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*
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* To anyone who acknowledges that this file is provided "AS IS"
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* without any express or implied warranty:
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* permission to use, copy, modify, and distribute this file
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* for any purpose is hereby granted without fee, provided that
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* the above copyright notice and this notice appears in all
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* copies, and that the name of i-cubed limited not be used in
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* advertising or publicity pertaining to distribution of the
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* software without specific, written prior permission.
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* i-cubed limited makes no representations about the suitability
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* of this software for any purpose.
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*
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* derived from "helas403/dlentry.S":
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*
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* Further changes to derive for the PPC405CR/GP/GPr/EX/EXr
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* by Michael Hamel ADInstruments Ltd 2008
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*/
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#include <rtems/asm.h>
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/*
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* The virtex ELF link scripts support three special sections:
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* .entry The actual entry point
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* .vectors The section containing the interrupt entry veneers.
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*/
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/*
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* Downloaded code loads the vectors separately to 0x00000100,
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* so .entry can be over 256 bytes.
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*
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* The other sections are linked in the following order:
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* .entry
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* .text
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* .data
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* .bss
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* see linker command file for section placement
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*
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* The initial stack is set to _ISR_Stack_area_end.
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*
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* All the entry veneer has to do is to clear the BSS.
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*/
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/*
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* GDB likes to have debugging information for the entry veneer.
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* Here was some DWARF information. IMD removed it, because we
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* could not check, whether it was still correct. Sorry.
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*/
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.section .entry
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PUBLIC_VAR (start)
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PUBLIC_VAR (download_entry)
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PUBLIC_VAR (__rtems_entry_point)
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SYM(start):
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SYM(download_entry):
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SYM(__rtems_entry_point):
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.extern SYM (boot_card)
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bl .startup /* First word is branch to reset_entry */
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/*---------------------------------------------------------------------------
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* Parameters from linker
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*--------------------------------------------------------------------------*/
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base_addr:
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toc_pointer:
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.long s.got
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bss_length:
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.long bss.size
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bss_addr:
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.long bss.start
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sbss_length:
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.long sbss.size
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sbss_addr:
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.long sbss.start
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stack_top:
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.long _ISR_Stack_area_end
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PUBLIC_VAR (text_addr)
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text_addr:
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.long text.start
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PUBLIC_VAR (text_length)
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text_length:
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.long text.size
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/*---------------------------------------------------------------------------
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* Reset_entry.
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*--------------------------------------------------------------------------*/
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.startup:
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/* Get entrypoint address in R1 so we can find linker variables */
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mflr r1
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/* Initialise procesor registers generally */
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bl init405
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/* Clear .bss and .sbss */
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bl bssclr
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/*-------------------------------------------------------------------
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* C_setup.
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*------------------------------------------------------------------*/
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lwz r1,stack_top - base_addr(r1) /* Now set R1 to stack_top */
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addi r1,r1,-56-4 /* start stack at text_addr - 56 */
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li r3,0
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stw r3, 0(r1) /* Clear stack chain */
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stw r3, 4(r1)
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stw r3, 8(r1)
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stw r3, 12(r1)
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bl __eabi /* Initialise EABI: sets up r2 & r13 */
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li r3, 0 /* command line */
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b SYM (boot_card) /* call the first C routine */
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/*---------------------------------------------------------------------------
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* bssclr.
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*--------------------------------------------------------------------------*/
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bssclr: lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */
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lwz r3,bss_length-base_addr(r1) /* bss length */
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srwi. r3,r3,2 /* div 4 to get # of words */
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li r0,0
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beq dosbss /* no bss */
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mtctr r3 /* set ctr reg */
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subi r2,r2,4
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clear_bss: stwu r0,4(r2)
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bdnz clear_bss /* decrement counter and loop */
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dosbss: lwz r2,sbss_addr-base_addr(r1) /* start of sbss set by loader */
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lwz r3,sbss_length-base_addr(r1) /* sbss length */
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slwi. r3,r3,2 /* div 4 to get # of words */
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subi r2,r2,4
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beqlr /* no sbss */
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mtctr r3 /* set ctr reg */
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clear_sbss: stwu r0,4(r2)
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bdnz clear_sbss /* decrement counter and loop */
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blr /* return */
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/*---------------------------------------------------------------------------
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* Generic 405 register setup
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*--------------------------------------------------------------------------*/
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init405:
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li r0, 0
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mtmsr r0
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mticcr r0
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mtdccr r0
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li r3,0x7FFC # 405EX-specific
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mtsgr r3 # Clear guarded mode on all storage except PCIe region
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mtsler r0 # Storage is all big-endian
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mtsu0r r0 # and uncompressed
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iccci r3,0 # Invalidate the instruction cache
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li r3,1 # Enable F800 0000 to FFFF FFFF
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oris r3,r3,0xC000 # Enable 0000 0000 to 0FFF FFFF
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mticcr r3
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isync
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li r3,0
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li r4,256 # 405 has 128 or 256 32-byte lines: do 256
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mtctr r4 # set loop ctr
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dcloop: dccci 0,r3 # invalidate line
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addi r3,r3,0x20 # bump to next line
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bdnz dcloop
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mtdcwr r0 # Select write-back caching
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lis r3,0xC000 # Enable 0000 0000 to 0FFF FFFF
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# mtdccr r3 # Enable data cache
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mtevpr r0
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mtesr r0
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mtxer r0
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lwarx r3,r0,r0 # get some data/set resv bit
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stwcx. r3,r0,r0 # store out and clear resv bit
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lis r3,0xDEAD
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ori r3,r3,0xBEEF # Make distintive uninitialised value
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mr r4, r3
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mr r5, r3
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mr r6, r3
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mr r7, r3
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mr r8, r3
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mr r9, r3
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mr r10, r3
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mr r11, r3
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mr r12, r3
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mr r13, r3
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mr r14, r3
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mr r15, r3
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mr r16, r3
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mr r17, r3
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mr r18, r3
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mr r19, r3
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mr r20, r3
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mr r21, r3
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mr r22, r3
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mr r23, r3
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mr r24, r3
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mr r25, r3
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mr r26, r3
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mr r27, r3
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mr r28, r3
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mr r29, r3
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mr r30, r3
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mr r31, r3
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blr
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.L_text_e:
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.comm environ,4,4
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