forked from Imagelibrary/rtems
294 lines
7.7 KiB
C
294 lines
7.7 KiB
C
/*
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* Simple interface to the PowerPC 405 MMU
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*
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* Michael Hamel ADInstruments 2008
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*
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*/
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#include <bsp.h>
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#include <libcpu/powerpc-utility.h>
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#include "mmu_405.h"
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#include <inttypes.h>
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/* #define qLogTLB */
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/* #define qLogTLBDetails */
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/*----------------------------- TLB handling -------------------------------- */
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/* The following are in assembler in mmu_405asm.S */
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extern void MMU_GetTLBEntry(uint8_t index, uint32_t* tagword, uint32_t* dataword, uint8_t* pid);
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extern void MMU_SetTLBEntry(uint8_t index, uint32_t hiword, uint32_t loword, uint8_t pid);
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extern void MMU_ClearTLBs(void);
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extern int16_t MMU_FindTLBEntry(uint32_t address);
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enum { kNTLBs = 64 }; /* for 403GCX and 405 */
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static bool sFreeTLBs[kNTLBs];
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static uint8_t sLastIndex = 0;
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static int sNInUse = 0;
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static void MMUFault(const char* what)
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/* Used for all setup faults; these can't really be ignored */
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{
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printk("\n>>>MMU fatal error %s\n",what);
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rtems_fatal_error_occurred(RTEMS_INTERNAL_ERROR);
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}
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static uint8_t AllocTLB(void)
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{
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uint8_t index;
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index = sLastIndex;
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do {
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index++;
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if (index == kNTLBs)
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index = 0;
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if (index == sLastIndex)
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MMUFault("TLB table full");
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} while (! sFreeTLBs[index]);
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sFreeTLBs[index] = false;
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sLastIndex = index;
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sNInUse++;
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return index;
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}
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static void FreeTLB(uint8_t index)
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{
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MMU_SetTLBEntry(index,0,0,0);
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sFreeTLBs[index] = true;
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sLastIndex = index-1;
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sNInUse--;
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}
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/*---------------------------- MMU operations ---------------------------------- */
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int DataMissException(BSP_Exception_frame *f, unsigned int vector);
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int InstructionMissException(BSP_Exception_frame *f, unsigned int vector);
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int InstructionFetchException(BSP_Exception_frame *f, unsigned int vector);
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void mmu_initialise(void);
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int mmu_get_tlb_count(void);
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uint8_t mmu_new_processID(void);
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uint8_t mmu_current_processID(void);
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void
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mmu_initialise(void)
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/* Clear the TLBs and set up exception handlers for the MMU miss handlers */
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{
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int i;
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MMU_ClearTLBs();
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for (i=0; i<kNTLBs; i++) {
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sFreeTLBs[i] = true;
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MMU_SetTLBEntry(i,0,0,0xFF);
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}
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ppc_exc_set_handler(ASM_ISI_VECTOR ,InstructionFetchException);
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ppc_exc_set_handler(ASM_BOOKE_ITLBMISS_VECTOR ,DataMissException);
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ppc_exc_set_handler(ASM_BOOKE_DTLBMISS_VECTOR ,InstructionMissException);
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}
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static void
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MakeTLBEntries(uint32_t startAt, uint32_t nBytes, bool EX, bool WR, bool I, uint8_t PID)
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{
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uint32_t mask, options, tagWord, dataWord;
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uint8_t index, sizeCode, pid;
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if ((startAt & 0x3FF) != 0)
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MMUFault("TLB entry not on 1K boundary");
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if ((nBytes & 0x3FF) != 0)
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MMUFault("TLB size not on 1K boundary");
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options = 0;
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if (EX) options += 0x200;
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if (WR) options += 0x100;
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if (I) options += 5;
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#ifdef qLogTLB
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printk("TLB: make entries for $%X bytes from $%X..$%X PID %d",nBytes, startAt, startAt+nBytes-1, PID);
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if (EX) printk(" EX");
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if (WR) printk(" WR");
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if (I) printk(" I");
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printk("\n");
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#endif
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while (nBytes > 0) {
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/* Find the largest block we can base on this address */
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mask = 0x3FF;
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sizeCode = 0;
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while (mask < nBytes && ((startAt & mask)==0) && sizeCode < 8) {
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mask = (mask<<2) + 3;
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sizeCode++;
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}
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mask >>= 2;
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sizeCode--;
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/* Make a TLB entry describing this, ZSEL=0 */
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tagWord = startAt | (sizeCode<<7) | 0x40;
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dataWord = startAt | options;
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index = AllocTLB();
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MMU_SetTLBEntry( index , tagWord, dataWord, PID);
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{
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/* Paranoia: check that we can read that back... */
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uint8_t tdex, oldpid;
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oldpid = mmu_current_processID();
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mmu_set_processID(PID);
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tdex = MMU_FindTLBEntry(startAt);
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mmu_set_processID(oldpid);
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if (tdex != index) {
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printk(" Add TLB %d: At %" PRIx32 " for $%" PRIx32
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" sizecode %d tagWord $%" PRIx32 " ",
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index, startAt, mask+1,sizeCode,tagWord);
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printk(" -- find failed, %d/%d!\n",tdex,index);
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MMU_GetTLBEntry(index, &tagWord, &dataWord, &pid);
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printk(" -- reads back $%" PRIx32 " : $%" PRIx32
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", PID %d\n",tagWord,dataWord,pid);
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} else {
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#ifdef qLogTLBDetails
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printk(" Add TLB %d: At %X for $%X sizecode %d tagWord $%X\n",index, startAt, mask+1,sizeCode,tagWord);
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#endif
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}
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}
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/* Subtract block from startAddr and nBytes */
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mask++; /* Convert to a byte count */
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startAt += mask;
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nBytes -= mask;
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}
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#ifdef qLogTLB
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printk(" %d in use\n",sNInUse);
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#endif
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}
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void
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mmu_remove_space(uint32_t startAt, uint32_t endAt)
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{
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int16_t index;
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int32_t size;
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uint32_t tagword, dataword, nBytes;
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uint8_t pid, sCode;
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nBytes = endAt - startAt;
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#ifdef qLogTLB
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printk("TLB: delete entries for $%X bytes from $%X\n",nBytes,startAt);
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#endif
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while (nBytes > 0) {
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index = MMU_FindTLBEntry( (uint32_t)startAt );
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size = 1024;
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if (index >= 0) {
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MMU_GetTLBEntry(index, &tagword, &dataword, &pid);
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if ((tagword & 0x40) == 0)
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MMUFault("Undefine failed: redundant entries?");
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if ((tagword & 0xFFFFFC00) != (uint32_t)startAt)
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MMUFault("Undefine not on TLB boundary");
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FreeTLB(index);
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sCode = (tagword >> 7) & 7;
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while (sCode > 0) {
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size <<= 2;
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sCode--;
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}
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#ifdef qLogTLBDetails
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printk(" Free TLB %d: At %X for $%X\n",index, startAt, size);
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#endif
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}
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startAt += size;
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nBytes -= size;
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}
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}
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void
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mmu_add_space(uint32_t startAddr, uint32_t endAddr, MMUAccessType permissions, uint8_t processID)
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/* Convert accesstype to write-enable, executable, and cache-inhibit bits */
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{
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bool EX, WR, I;
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EX = false;
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WR = false;
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I = false;
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switch (permissions) {
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case executable : EX = true; break;
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case readOnlyData : break;
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case readOnlyNoCache : I = true; break;
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case readWriteData : WR = true; break;
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case readWriteNoCache : WR = true; I= true; break;
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case readWriteExecutable: WR = true; EX = true; break;
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}
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MakeTLBEntries( (uint32_t)startAddr, (uint32_t)(endAddr-startAddr+1), EX, WR, I, processID);
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}
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int
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mmu_get_tlb_count(void)
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{
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return sNInUse;
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}
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/*---------------------------- CPU process ID handling ----------------------------------
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* Really dumb system where we just hand out sequential numbers and eventually fail
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* As long as we only use 8-9 processes this isn't a problem */
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static uint8_t sNextPID = 1;
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#define SPR_PID 0x3B1
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uint8_t mmu_new_processID(void)
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{
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return sNextPID++;
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}
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void mmu_free_processID(uint8_t freeThis)
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{
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}
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uint8_t mmu_current_processID(void)
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{
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return PPC_SPECIAL_PURPOSE_REGISTER(SPR_PID);
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}
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uint8_t mmu_set_processID(uint8_t newID)
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{
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uint8_t prev = mmu_current_processID();
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PPC_SET_SPECIAL_PURPOSE_REGISTER(SPR_PID,newID);
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return prev;
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}
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/* ------------------ Fault handlers ------------------ */
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#define SPR_ESR 0x3D4
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#define SPR_DEAR 0x3D5
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enum { kESR_DST = 0x00800000 };
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int DataMissException(BSP_Exception_frame *f, unsigned int vector)
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{
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uint32_t addr, excSyn;
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addr = PPC_SPECIAL_PURPOSE_REGISTER(SPR_DEAR);
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excSyn = PPC_SPECIAL_PURPOSE_REGISTER(SPR_ESR);
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if (excSyn & kESR_DST) printk("\n---Data write to $%" PRIx32
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" attempted at $%" PRIxPTR "\n",addr,f->EXC_SRR0);
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else printk("\n---Data read from $%" PRIx32 " attempted at $%"
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PRIxPTR "\n",addr,f->EXC_SRR0);
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return -1;
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}
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int InstructionMissException(BSP_Exception_frame *f, unsigned int vector)
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{
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printk("\n---Instruction fetch attempted from $%" PRIxPTR ", no TLB exists\n",
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f->EXC_SRR0);
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return -1;
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}
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int InstructionFetchException(BSP_Exception_frame *f, unsigned int vector)
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{
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printk("\n---Instruction fetch attempted from $%" PRIxPTR
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", TLB is no-execute\n",f->EXC_SRR0);
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return -1;
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}
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