forked from Imagelibrary/rtems
2afb22b7e1
A speciality of the RTEMS build system was the make preinstall step. It copied header files from arbitrary locations into the build tree. The header files were included via the -Bsome/build/tree/path GCC command line option. This has at least seven problems: * The make preinstall step itself needs time and disk space. * Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error. * There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult. * The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit. * An introduction of a new build system is difficult. * Include paths specified by the -B option are system headers. This may suppress warnings. * The parallel build had sporadic failures on some hosts. This patch removes the make preinstall step. All installed header files are moved to dedicated include directories in the source tree. Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc, etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g. erc32, imx, qoriq, etc. The new cpukit include directories are: * cpukit/include * cpukit/score/cpu/@RTEMS_CPU@/include * cpukit/libnetworking The new BSP include directories are: * bsps/include * bsps/@RTEMS_CPU@/include * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include There are build tree include directories for generated files. The include directory order favours the most general header file, e.g. it is not possible to override general header files via the include path order. The "bootstrap -p" option was removed. The new "bootstrap -H" option should be used to regenerate the "headers.am" files. Update #3254.
46 lines
1.6 KiB
C
46 lines
1.6 KiB
C
/**
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* @file
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* @ingroup i386_irq
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* @brief
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*/
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/* irq_asm.h
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*
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* This include file has defines to represent some contant used
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* to program and manage the Intel 8259 interrupt controller
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*
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*
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* COPYRIGHT (c) 1998 valette@crf.canon.fr
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*
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* Copyright (c) 2016 Chris Johns <chrisj@rtems.org>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef __I8259S_H__
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#define __I8259S_H__
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#define BSP_ASM_IRQ_VECTOR_BASE 0x20
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/** @brief PIC's command and mask registers */
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#define PIC_MASTER_COMMAND_IO_PORT 0x20 ///< Master PIC command register
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#define PIC_SLAVE_COMMAND_IO_PORT 0xa0 ///< Slave PIC command register
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#define PIC_MASTER_IMR_IO_PORT 0x21 ///< Master PIC Interrupt Mask Register
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#define PIC_SLAVE_IMR_IO_PORT 0xa1 ///< Slave PIC Interrupt Mask Register
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/** @brief Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
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#define PIC_EOSI 0x60 ///< End of Specific Interrupt (EOSI)
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#define PIC_EOI 0x20 ///< Generic End of Interrupt (EOI)
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/* Operation control word type 3. Bit 3 (0x08) must be set. Even address. */
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#define PIC_OCW3_RIS 0x01 /* 1 = read IS, 0 = read IR */
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#define PIC_OCW3_RR 0x02 /* register read */
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#define PIC_OCW3_P 0x04 /* poll mode command */
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/* 0x08 must be 1 to select OCW3 vs OCW2 */
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#define PIC_OCW3_SEL 0x08 /* must be 1 */
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/* 0x10 must be 0 to select OCW3 vs ICW1 */
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#define PIC_OCW3_SMM 0x20 /* special mode mask */
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#define PIC_OCW3_ESMM 0x40 /* enable SMM */
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#endif
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