forked from Imagelibrary/rtems
379 lines
14 KiB
C
379 lines
14 KiB
C
/** @file
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based on Ti HalCoGen generated file
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*/
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/*
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* Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <stdint.h>
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#include <stdbool.h>
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#include <bsp/tms570.h>
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#include <bsp/tms570-pinmux.h>
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#include <bsp/tms570_selftest.h>
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#include <bsp/tms570_hwinit.h>
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/**
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* @brief Setup all system PLLs (HCG:setupPLL)
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*
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*/
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void tms570_pll_init( void )
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{
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uint32_t pll12_dis = 0x42;
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/* Disable PLL1 and PLL2 */
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TMS570_SYS1.CSDISSET = pll12_dis;
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/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
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while ( ( TMS570_SYS1.CSDIS & pll12_dis ) != pll12_dis ) {
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/* Wait */
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}
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/* Clear Global Status Register */
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TMS570_SYS1.GLBSTAT = TMS570_SYS1_GLBSTAT_FBSLIP |
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TMS570_SYS1_GLBSTAT_RFSLIP |
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TMS570_SYS1_GLBSTAT_OSCFAIL;
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/** - Configure PLL control registers */
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/** @b Initialize @b Pll1: */
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/* Setup pll control register 1 */
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TMS570_SYS1.PLLCTL1 = TMS570_SYS1_PLLCTL1_ROS * 0 |
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TMS570_SYS1_PLLCTL1_MASK_SLIP( 1 ) |
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TMS570_SYS1_PLLCTL1_PLLDIV( 0x1f ) | /* max value */
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TMS570_SYS1_PLLCTL1_ROF * 0 |
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TMS570_SYS1_PLLCTL1_REFCLKDIV( 6 - 1 ) |
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TMS570_SYS1_PLLCTL1_PLLMUL( ( 120 - 1 ) << 8 );
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/* Setup pll control register 2 */
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TMS570_SYS1.PLLCTL2 = TMS570_SYS1_PLLCTL2_FMENA * 0 |
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TMS570_SYS1_PLLCTL2_SPREADINGRATE( 255 ) |
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TMS570_SYS1_PLLCTL2_MULMOD( 7 ) |
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TMS570_SYS1_PLLCTL2_ODPLL( 2 - 1 ) |
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TMS570_SYS1_PLLCTL2_SPR_AMOUNT( 61 );
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/** @b Initialize @b Pll2: */
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/* Setup pll2 control register */
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TMS570_SYS2.PLLCTL3 = TMS570_SYS2_PLLCTL3_ODPLL2( 2 - 1 ) |
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TMS570_SYS2_PLLCTL3_PLLDIV2( 0x1F ) | /* max value */
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TMS570_SYS2_PLLCTL3_REFCLKDIV2( 6 - 1 ) |
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TMS570_SYS2_PLLCTL3_PLLMUL2( ( 120 - 1 ) << 8 );
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/** - Enable PLL(s) to start up or Lock */
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TMS570_SYS1.CSDIS = 0x00000000 | /* CLKSR0 on */
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0x00000000 | /* CLKSR1 on */
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0x00000008 | /* CLKSR3 off */
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0x00000000 | /* CLKSR4 on */
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0x00000000 | /* CLKSR5 on */
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0x00000000 | /* CLKSR6 on */
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0x00000080; /* CLKSR7 off */
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}
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/**
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* @brief Adjust Low-Frequency (LPO) oscilator (HCG:trimLPO)
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*
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*/
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/* SourceId : SYSTEM_SourceId_002 */
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/* DesignId : SYSTEM_DesignId_002 */
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/* Requirements : HL_SR468 */
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void tms570_trim_lpo_init( void )
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{
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/** @b Initialize Lpo: */
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/** Load TRIM values from OTP if present else load user defined values */
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/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
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TMS570_SYS1.LPOMONCTL = TMS570_SYS1_LPOMONCTL_BIAS_ENABLE |
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TMS570_SYS1_LPOMONCTL_OSCFRQCONFIGCNT * 0 |
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TMS570_SYS1_LPOMONCTL_HFTRIM( 16 ) |
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16; /* LFTRIM */
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}
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/* FIXME */
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enum tms570_flash_power_modes {
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TMS570_FLASH_SYS_SLEEP = 0U, /**< Alias for flash bank power mode sleep */
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TMS570_FLASH_SYS_STANDBY = 1U, /**< Alias for flash bank power mode standby */
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TMS570_FLASH_SYS_ACTIVE = 3U /**< Alias for flash bank power mode active */
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};
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enum tms570_system_clock_source {
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TMS570_SYS_CLK_SRC_OSC = 0U, /**< Alias for oscillator clock Source */
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TMS570_SYS_CLK_SRC_PLL1 = 1U, /**< Alias for Pll1 clock Source */
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TMS570_SYS_CLK_SRC_EXTERNAL1 = 3U, /**< Alias for external clock Source */
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TMS570_SYS_CLK_SRC_LPO_LOW = 4U, /**< Alias for low power oscillator low clock Source */
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TMS570_SYS_CLK_SRC_LPO_HIGH = 5U, /**< Alias for low power oscillator high clock Source */
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TMS570_SYS_CLK_SRC_PLL2 = 6U, /**< Alias for Pll2 clock Source */
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TMS570_SYS_CLK_SRC_EXTERNAL2 = 7U, /**< Alias for external 2 clock Source */
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TMS570_SYS_CLK_SRC_VCLK = 9U /**< Alias for synchronous VCLK1 clock Source */
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};
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/**
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* @brief Setup Flash memory parameters and timing (HCG:setupFlash)
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*
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*/
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/* SourceId : SYSTEM_SourceId_003 */
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/* DesignId : SYSTEM_DesignId_003 */
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/* Requirements : HL_SR457 */
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void tms570_flash_init( void )
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{
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/** - Setup flash read mode, address wait states and data wait states */
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TMS570_FLASH.FRDCNTL = TMS570_FLASH_FRDCNTL_RWAIT( 3 ) |
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TMS570_FLASH_FRDCNTL_ASWSTEN |
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TMS570_FLASH_FRDCNTL_ENPIPE;
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/** - Setup flash access wait states for bank 7 */
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TMS570_FLASH.FSMWRENA = TMS570_FLASH_FSMWRENA_WR_ENA( 0x5 );
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TMS570_FLASH.EEPROMCONFIG = TMS570_FLASH_EEPROMCONFIG_EWAIT( 3 ) |
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TMS570_FLASH_EEPROMCONFIG_AUTOSUSP_EN * 0 |
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TMS570_FLASH_EEPROMCONFIG_AUTOSTART_GRACE( 2 );
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/** - Disable write access to flash state machine registers */
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TMS570_FLASH.FSMWRENA = TMS570_FLASH_FSMWRENA_WR_ENA( 0xA );
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/** - Setup flash bank power modes */
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TMS570_FLASH.FBFALLBACK = TMS570_FLASH_FBFALLBACK_BANKPWR7(
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TMS570_FLASH_SYS_ACTIVE ) |
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TMS570_FLASH_FBFALLBACK_BANKPWR1(
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TMS570_FLASH_SYS_ACTIVE ) |
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TMS570_FLASH_FBFALLBACK_BANKPWR0(
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TMS570_FLASH_SYS_ACTIVE );
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}
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/**
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* @brief Power-up all peripherals and enable their clocks (HCG:periphInit)
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*
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*/
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/* SourceId : SYSTEM_SourceId_004 */
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/* DesignId : SYSTEM_DesignId_004 */
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/* Requirements : HL_SR470 */
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void tms570_periph_init( void )
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{
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/** - Disable Peripherals before peripheral powerup*/
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TMS570_SYS1.CLKCNTL &= ~TMS570_SYS1_CLKCNTL_PENA;
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/** - Release peripherals from reset and enable clocks to all peripherals */
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/** - Power-up all peripherals */
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TMS570_PCR.PSPWRDWNCLR0 = 0xFFFFFFFFU;
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TMS570_PCR.PSPWRDWNCLR1 = 0xFFFFFFFFU;
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TMS570_PCR.PSPWRDWNCLR2 = 0xFFFFFFFFU;
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TMS570_PCR.PSPWRDWNCLR3 = 0xFFFFFFFFU;
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/** - Enable Peripherals */
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TMS570_SYS1.CLKCNTL |= TMS570_SYS1_CLKCNTL_PENA;
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}
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/**
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* @brief Setup chip clocks including to wait for PLLs locks (HCG:mapClocks)
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*
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*/
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/* SourceId : SYSTEM_SourceId_005 */
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/* DesignId : SYSTEM_DesignId_005 */
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/* Requirements : HL_SR469 */
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void tms570_map_clock_init( void )
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{
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uint32_t sys_csvstat, sys_csdis;
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/** @b Initialize @b Clock @b Tree: */
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/** - Disable / Enable clock domain */
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TMS570_SYS1.CDDIS = ( 0U << 4U ) | /* AVCLK 1 OFF */
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( 0U << 5U ) | /* AVCLK 2 OFF */
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( 0U << 8U ) | /* VCLK3 OFF */
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( 0U << 9U ) | /* VCLK4 OFF */
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( 1U << 10U ) | /* AVCLK 3 OFF */
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( 0U << 11U ); /* AVCLK 4 OFF */
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/* Work Around for Errata SYS#46:
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*
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* Errata Description:
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* Clock Source Switching Not Qualified with Clock Source Enable And Clock Source Valid
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* Workaround:
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* Always check the CSDIS register to make sure the clock source is turned on and check
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* the CSVSTAT register to make sure the clock source is valid. Then write to GHVSRC to switch the clock.
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*/
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/** - Wait for until clocks are locked */
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sys_csvstat = TMS570_SYS1.CSVSTAT;
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sys_csdis = TMS570_SYS1.CSDIS;
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while ( ( sys_csvstat & ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) !=
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( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) {
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sys_csvstat = TMS570_SYS1.CSVSTAT;
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sys_csdis = TMS570_SYS1.CSDIS;
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} /* Wait */
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/* Now the PLLs are locked and the PLL outputs can be sped up */
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/* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */
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TMS570_SYS1.PLLCTL1 =
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( TMS570_SYS1.PLLCTL1 & ~TMS570_SYS1_PLLCTL1_PLLDIV( 0x1F ) ) |
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TMS570_SYS1_PLLCTL1_PLLDIV( 1 - 1 );
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/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
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TMS570_SYS2.PLLCTL3 =
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( TMS570_SYS2.PLLCTL3 & ~TMS570_SYS2_PLLCTL3_PLLDIV2( 0x1F ) ) |
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TMS570_SYS2_PLLCTL3_PLLDIV2( 1 - 1 );
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/* Enable/Disable Frequency modulation */
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TMS570_SYS1.PLLCTL2 &= ~TMS570_SYS1_PLLCTL2_FMENA;
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/** - Map device clock domains to desired sources and configure top-level dividers */
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/** - All clock domains are working off the default clock sources until now */
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/** - The below assignments can be easily modified using the HALCoGen GUI */
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/** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */
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TMS570_SYS1.GHVSRC = TMS570_SYS1_GHVSRC_GHVWAKE( TMS570_SYS_CLK_SRC_OSC ) |
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TMS570_SYS1_GHVSRC_HVLPM( TMS570_SYS_CLK_SRC_OSC ) |
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TMS570_SYS1_GHVSRC_GHVSRC( TMS570_SYS_CLK_SRC_PLL1 );
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/** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */
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TMS570_SYS1.CLKCNTL =
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( TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLK2R( 0xF ) ) |
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TMS570_SYS1_CLKCNTL_VCLK2R( 1 );
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TMS570_SYS1.CLKCNTL =
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( TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLKR( 0xF ) ) |
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TMS570_SYS1_CLKCNTL_VCLKR( 1 );
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TMS570_SYS2.CLK2CNTRL =
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( TMS570_SYS2.CLK2CNTRL & ~TMS570_SYS2_CLK2CNTRL_VCLK3R( 0xF ) ) |
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TMS570_SYS2_CLK2CNTRL_VCLK3R( 1 );
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TMS570_SYS2.CLK2CNTRL = ( TMS570_SYS2.CLK2CNTRL & 0xFFFFF0FFU ) |
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( 1U << 8U ); /* FIXME: unknown in manual*/
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/** - Setup RTICLK1 and RTICLK2 clocks */
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TMS570_SYS1.RCLKSRC = ( 1U << 24U ) |
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( TMS570_SYS_CLK_SRC_VCLK << 16U ) | /* FIXME: not in manual */
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TMS570_SYS1_RCLKSRC_RTI1DIV( 1 ) |
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TMS570_SYS1_RCLKSRC_RTI1SRC( TMS570_SYS_CLK_SRC_VCLK );
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/** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */
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TMS570_SYS1.VCLKASRC =
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TMS570_SYS1_VCLKASRC_VCLKA2S( TMS570_SYS_CLK_SRC_VCLK ) |
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TMS570_SYS1_VCLKASRC_VCLKA1S( TMS570_SYS_CLK_SRC_VCLK );
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TMS570_SYS2.VCLKACON1 = TMS570_SYS2_VCLKACON1_VCLKA4R( 1 - 1 ) |
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TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS * 0 |
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TMS570_SYS2_VCLKACON1_VCLKA4S(
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TMS570_SYS_CLK_SRC_VCLK ) |
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TMS570_SYS2_VCLKACON1_VCLKA3R( 1 - 1 ) |
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TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS * 0 |
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TMS570_SYS2_VCLKACON1_VCLKA3S(
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TMS570_SYS_CLK_SRC_VCLK );
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}
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/**
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* @brief TMS570 system hardware initialization (HCG:systemInit)
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*
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*/
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/* SourceId : SYSTEM_SourceId_006 */
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/* DesignId : SYSTEM_DesignId_006 */
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/* Requirements : HL_SR471 */
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void tms570_system_hw_init( void )
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{
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uint32_t efc_check_status;
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/* Configure PLL control registers and enable PLLs.
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* The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock.
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* This initialization sequence performs all the tasks that are not
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* required to be done at full application speed while the PLL locks.
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*/
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tms570_pll_init();
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/* Run eFuse controller start-up checks and start eFuse controller ECC self-test.
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* This includes a check for the eFuse controller error outputs to be stuck-at-zero.
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*/
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efc_check_status = tms570_efc_check();
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/* Enable clocks to peripherals and release peripheral reset */
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tms570_periph_init();
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/* Configure device-level multiplexing and I/O multiplexing */
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tms570_pinmux_init();
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/* Enable external memory interface */
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TMS570_SYS1.GPREG1 |= TMS570_SYS1_GPREG1_EMIF_FUNC;
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if ( efc_check_status == 0U ) {
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/* Wait for eFuse controller self-test to complete and check results */
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if ( tms570_efc_check_self_test() == false ) { /* eFuse controller ECC logic self-test failed */
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bsp_selftest_fail_notification( EFCCHECK_FAIL1 ); /* device operation is not reliable */
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}
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} else if ( efc_check_status == 2U ) {
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/* Wait for eFuse controller self-test to complete and check results */
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if ( tms570_efc_check_self_test() == false ) { /* eFuse controller ECC logic self-test failed */
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bsp_selftest_fail_notification( EFCCHECK_FAIL1 ); /* device operation is not reliable */
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} else {
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bsp_selftest_fail_notification( EFCCHECK_FAIL2 );
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}
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} else {
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/* Empty */
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}
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/** - Set up flash address and data wait states based on the target CPU clock frequency
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* The number of address and data wait states for the target CPU clock frequency are specified
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* in the specific part's datasheet.
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*/
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tms570_flash_init();
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/** - Configure the LPO such that HF LPO is as close to 10MHz as possible */
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tms570_trim_lpo_init();
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/** - Wait for PLLs to start up and map clock domains to desired clock sources */
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tms570_map_clock_init();
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/** - set ECLK pins functional mode */
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TMS570_SYS1.SYSPC1 = 0U;
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/** - set ECLK pins default output value */
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TMS570_SYS1.SYSPC4 = 0U;
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/** - set ECLK pins output direction */
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TMS570_SYS1.SYSPC2 = 1U;
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/** - set ECLK pins open drain enable */
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TMS570_SYS1.SYSPC7 = 0U;
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/** - set ECLK pins pullup/pulldown enable */
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TMS570_SYS1.SYSPC8 = 0U;
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/** - set ECLK pins pullup/pulldown select */
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TMS570_SYS1.SYSPC9 = 1U;
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/** - Setup ECLK */
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TMS570_SYS1.ECPCNTL = TMS570_SYS1_ECPCNTL_ECPSSEL * 0 |
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TMS570_SYS1_ECPCNTL_ECPCOS * 0 |
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TMS570_SYS1_ECPCNTL_ECPDIV( 8 - 1 );
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}
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#if 0
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errata_PBIST_4
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vimInit
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#endif
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