forked from Imagelibrary/rtems
0d362ff397
Pass current processor control via parameter since it may be already available at the caller side.
67 lines
1.4 KiB
C
67 lines
1.4 KiB
C
/*
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* Copyright (c) 2013, 2018 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <info@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <assert.h>
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#include <rtems/score/smpimpl.h>
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#include <libcpu/arm-cp15.h>
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#include <bsp/irq.h>
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static void bsp_inter_processor_interrupt(void *arg)
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{
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_SMP_Inter_processor_interrupt_handler(_Per_CPU_Get());
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}
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uint32_t _CPU_SMP_Initialize(void)
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{
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return arm_gic_irq_processor_count();
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}
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void _CPU_SMP_Finalize_initialization(uint32_t cpu_count)
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{
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if (cpu_count > 0) {
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rtems_status_code sc;
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sc = rtems_interrupt_handler_install(
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ARM_GIC_IRQ_SGI_0,
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"IPI",
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RTEMS_INTERRUPT_UNIQUE,
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bsp_inter_processor_interrupt,
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NULL
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);
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assert(sc == RTEMS_SUCCESSFUL);
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#if defined(BSP_DATA_CACHE_ENABLED) || defined(BSP_INSTRUCTION_CACHE_ENABLED)
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/* Enable unified L2 cache */
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rtems_cache_enable_data();
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#endif
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}
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}
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void _CPU_SMP_Prepare_start_multitasking( void )
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{
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/* Do nothing */
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}
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void _CPU_SMP_Send_interrupt( uint32_t target_processor_index )
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{
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arm_gic_irq_generate_software_irq(
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ARM_GIC_IRQ_SGI_0,
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ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
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(uint8_t) (1U << target_processor_index)
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);
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}
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