forked from Imagelibrary/rtems
f9648baf65
The small page MMU support reduces the granularity for memory settings through the MMU from 1MiB sections to 4KiB small pages. Enable it by default on the realview_pbx_a9_qemu BSP.
134 lines
3.6 KiB
C
134 lines
3.6 KiB
C
/*
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* Copyright (c) 2010-2019 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems.h>
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#include <libcpu/arm-cp15.h>
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#include <bspopts.h>
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/*
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* Translation table modification requires to propagate
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* information to memory and other cores.
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*
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* Algorithm follows example found in the section
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*
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* B3.10.1 General TLB maintenance requirements
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* TLB maintenance operations and the memory order model
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*
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* of ARM Architecture Reference Manual
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* ARMv7-A and ARMv7-R edition
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* ARM DDI 0406C.b (ID072512)
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*/
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static uint32_t set_translation_table_entries(
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const void *begin,
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const void *end,
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uint32_t section_flags
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)
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{
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uint32_t *ttb;
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#ifdef ARM_MMU_USE_SMALL_PAGES
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uint32_t *pt;
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uint32_t flags;
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#endif
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uint32_t istart;
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uint32_t iend;
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uint32_t index_mask;
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uint32_t section_flags_of_first_entry;
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uint32_t i;
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uint32_t *modified_begin;
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size_t modified_size;
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ttb = arm_cp15_get_translation_table_base();
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#ifdef ARM_MMU_USE_SMALL_PAGES
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pt = &ttb[ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT];
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istart = ARM_MMU_SMALL_PAGE_GET_INDEX(begin);
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iend = ARM_MMU_SMALL_PAGE_GET_INDEX(ARM_MMU_SMALL_PAGE_MVA_ALIGN_UP(end));
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index_mask = (1U << (32 - ARM_MMU_SMALL_PAGE_BASE_SHIFT)) - 1U;
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section_flags_of_first_entry = ARM_MMU_SMALL_PAGE_FLAGS_TO_SECT(pt[istart])
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| ARM_MMU_PAGE_TABLE_FLAGS_TO_SECT(ttb[ARM_MMU_SECT_GET_INDEX(begin)]);
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modified_begin = &pt[istart];
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flags = ARM_MMU_SECT_FLAGS_TO_SMALL_PAGE(section_flags);
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#else
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istart = ARM_MMU_SECT_GET_INDEX(begin);
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iend = ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(end));
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index_mask = (1U << (32 - ARM_MMU_SECT_BASE_SHIFT)) - 1U;
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section_flags_of_first_entry = ttb[istart];
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modified_begin = &ttb[istart];
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#endif
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modified_size = 0;
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for ( i = istart; i != iend; i = (i + 1U) & index_mask ) {
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uint32_t pa;
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#ifdef ARM_MMU_USE_SMALL_PAGES
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pa = i << ARM_MMU_SMALL_PAGE_BASE_SHIFT;
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pt[i] = pa | flags;
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modified_size += ARM_MMU_SMALL_PAGE_TABLE_ENTRY_SIZE;
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#else
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pa = i << ARM_MMU_SECT_BASE_SHIFT;
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ttb[i] = pa | section_flags;
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modified_size += ARM_MMU_TRANSLATION_TABLE_ENTRY_SIZE;
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#endif
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}
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if ((arm_cp15_get_control() & (ARM_CP15_CTRL_C | ARM_CP15_CTRL_M)) != 0) {
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rtems_cache_flush_multiple_data_lines(modified_begin, modified_size);
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}
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_ARM_Data_synchronization_barrier();
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for ( i = istart; i != iend; i = (i + 1U) & index_mask ) {
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void *mva;
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#ifdef ARM_MMU_USE_SMALL_PAGES
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mva = (void *) (i << ARM_MMU_SMALL_PAGE_BASE_SHIFT);
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#else
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mva = (void *) (i << ARM_MMU_SECT_BASE_SHIFT);
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#endif
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#if defined(__ARM_ARCH_7A__)
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/*
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* Bit 31 needs to be 1 to indicate the register implements the
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* Multiprocessing Extensions register format and the U (bit 30)
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* is 0.
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*/
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#define MPIDR_MX_FMT (1 << 31)
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#define MPIDR_UP (1 << 30)
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const uint32_t mpidr = arm_cp15_get_multiprocessor_affinity();
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if ((mpidr & (MPIDR_MX_FMT | MPIDR_UP)) == MPIDR_MX_FMT) {
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arm_cp15_tlb_invalidate_entry_all_asids(mva);
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}
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else
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#endif
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{
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arm_cp15_tlb_instruction_invalidate_entry(mva);
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arm_cp15_tlb_data_invalidate_entry(mva);
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}
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}
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_ARM_Data_synchronization_barrier();
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_ARM_Instruction_synchronization_barrier();
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return section_flags_of_first_entry;
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}
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uint32_t arm_cp15_set_translation_table_entries(
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const void *begin,
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const void *end,
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uint32_t section_flags
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)
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{
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return set_translation_table_entries(begin, end, section_flags);
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}
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