forked from Imagelibrary/rtems
134 lines
3.4 KiB
C
134 lines
3.4 KiB
C
/**
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* @file
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*
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* @ingroup RTEMSBSPsARMLPC24XX
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*
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* @brief BSP start EMC static memory configuration.
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*/
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/*
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* Copyright (c) 2011 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Obere Lagerstr. 30
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <bsp/start-config.h>
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#include <bsp/lpc24xx.h>
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BSP_START_DATA_SECTION const lpc24xx_emc_static_chip_config
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lpc24xx_start_config_emc_static_chip [] = {
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#if defined(LPC24XX_EMC_M29W160E)
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/*
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* Static Memory 1: Numonyx M29W160EB
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*
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* 1 clock cycle = 1/72MHz = 13.9ns
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*/
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{
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.chip_select = (volatile lpc_emc_static *) EMC_STA_BASE_1,
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.config = {
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/*
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* 16 bit, page mode disabled, active LOW chip select, extended wait
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* disabled, writes not protected, byte lane state LOW/LOW (!).
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*/
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.config = 0x81,
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/* 1 clock cycles delay from the chip select 1 to the write enable */
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.waitwen = 0,
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/*
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* 0 clock cycles delay from the chip select 1 or address change
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* (whichever is later) to the output enable
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*/
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.waitoen = 0,
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/* 7 clock cycles delay from the chip select 1 to the read access */
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.waitrd = 0x6,
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/*
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* 32 clock cycles delay for asynchronous page mode sequential accesses
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*/
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.waitpage = 0x1f,
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/* 5 clock cycles delay from the chip select 1 to the write access */
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.waitwr = 0x3,
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/* 16 bus turnaround cycles */
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.waitrun = 0xf
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}
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}
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#elif defined(LPC24XX_EMC_M29W320E70)
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/* Static Memory 0: M29W320E70 */
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{
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.chip_select = (volatile lpc_emc_static *) EMC_STA_BASE_0,
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.config = {
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/*
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* 16 bit, page mode disabled, active LOW chip select, extended wait
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* disabled, writes not protected, byte lane state LOW/LOW.
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*/
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.config = 0x81,
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/* 30ns (tWHWL) */
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.waitwen = LPC24XX_PS_TO_EMCCLK(30000, 1),
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/* 0ns */
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.waitoen = LPC24XX_PS_TO_EMCCLK(0, 1),
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/* 70ns (tAVQV, tELQV) */
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.waitrd = LPC24XX_PS_TO_EMCCLK(70000, 1),
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/* 70ns (tAVQV, tELQV) */
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.waitpage = LPC24XX_PS_TO_EMCCLK(70000, 1),
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/* max(30ns (tWHWL) + 45ns (tWLWH), 70ns (tAVAV)) */
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.waitwr = LPC24XX_PS_TO_EMCCLK(75000, 2),
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/* 25ns (tEHQZ) */
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.waitrun = LPC24XX_PS_TO_EMCCLK(25000, 1)
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}
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}
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#elif defined(LPC24XX_EMC_SST39VF3201)
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/* Static Memory 0: SST39VF3201 */
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{
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.chip_select = (volatile lpc_emc_static *) EMC_STA_BASE_0,
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.config = {
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/*
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* 16 bit, page mode disabled, active LOW chip select, extended wait
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* disabled, writes not protected, byte lane state LOW/LOW.
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*/
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.config = 0x81,
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/* 0ns (tCS, tAS) */
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.waitwen = LPC24XX_PS_TO_EMCCLK(0, 1),
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/* 0ns (tOES) */
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.waitoen = LPC24XX_PS_TO_EMCCLK(0, 1),
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/* 70ns (tRC) */
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.waitrd = LPC24XX_PS_TO_EMCCLK(70000, 1),
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/* 70ns (tRC) */
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.waitpage = LPC24XX_PS_TO_EMCCLK(70000, 1),
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/* 20ns (tCHZ, TOHZ) */
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.waitwr = LPC24XX_PS_TO_EMCCLK(20000, 2),
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/* 20ns (tCHZ, TOHZ) */
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.waitrun = LPC24XX_PS_TO_EMCCLK(20000, 1)
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}
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}
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#endif
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};
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BSP_START_DATA_SECTION const size_t
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lpc24xx_start_config_emc_static_chip_count =
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sizeof(lpc24xx_start_config_emc_static_chip)
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/ sizeof(lpc24xx_start_config_emc_static_chip [0]);
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