forked from Imagelibrary/rtems
86 lines
2.9 KiB
ArmAsm
86 lines
2.9 KiB
ArmAsm
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSBSPsSPARCShared
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*
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* @brief This assembler source file contains the LEON3-specific
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* bsp_idle_thread() implementation.
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*/
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/*
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* Idle Thread Body
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*
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* This routine puts LEON3 in power-down mode.
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*
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* COPYRIGHT (c) 2004.
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* Gaisler Research.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <rtems/asm.h>
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/*
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* LEON specific power-down function
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*
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* This implementation contains the workaround for the GR712RC
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* power-down errata described in GR712RC-UM, version 2.16, section
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* 1.7.8. The workaround is compatible with other LEON3 components.
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*/
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.align 4
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PUBLIC(bsp_idle_thread)
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PUBLIC(leon3_power_down_loop)
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SYM(bsp_idle_thread):
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SYM(leon3_power_down_loop):
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pwdloop:
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/*
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* Address 0xfffffff0 is the read-only AHB plug & play region at
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* least for the UT699, GR712RC, and GR740.
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*/
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set 0xfffffff0, %o0
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/*
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* Make sure the following two instructions are in one cache line.
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* This ensures that the instructions are fetched from the
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* instruction cache when the processor leaves power-down mode
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* (unless a SEU occurs in the instruction cache line).
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*
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* Use a load which bypasses the MMU and cache (ASI 0x1c).
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*/
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.align 32
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mov %g0, %asr19
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lda [%o0] 0x1c, %g0
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/*
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* Place the branch far enough away from the preceding load, to make
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* sure the preceding load is executed before the branch to prevent
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* an instruction fetch from memory.
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*/
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.align 32
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ba,a pwdloop
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nop
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