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105 lines
3.4 KiB
Perl
105 lines
3.4 KiB
Perl
@c
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@c COPYRIGHT (c) 1988-2002.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c
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@c $Id$
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@c
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@chapter Memory Model
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@section Introduction
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A processor may support any combination of memory
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models ranging from pure physical addressing to complex demand
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paged virtual memory systems. RTEMS supports a flat memory
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model which ranges contiguously over the processor's allowable
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address space. RTEMS does not support segmentation or virtual
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memory of any kind. The appropriate memory model for RTEMS
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provided by the targeted processor and related characteristics
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of that model are described in this chapter.
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@section Flat Memory Model
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The SPARC architecture supports a flat 32-bit address
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space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4
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gigabytes). Each address is represented by a 32-bit value and
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is byte addressable. The address may be used to reference a
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single byte, half-word (2-bytes), word (4 bytes), or doubleword
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(8 bytes). Memory accesses within this address space are
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performed in big endian fashion by the SPARC. Memory accesses
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which are not properly aligned generate a "memory address not
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aligned" trap (type number 7). The following table lists the
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alignment requirements for a variety of data accesses:
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@ifset use-ascii
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@example
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@group
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+--------------+-----------------------+
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| Data Type | Alignment Requirement |
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+--------------+-----------------------+
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| byte | 1 |
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| half-word | 2 |
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| word | 4 |
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| doubleword | 8 |
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+--------------+-----------------------+
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@end group
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@end example
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@end ifset
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@ifset use-tex
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@sp 1
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@tex
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\centerline{\vbox{\offinterlineskip\halign{
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\vrule\strut#&
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\hbox to 1.75in{\enskip\hfil#\hfil}&
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\vrule#&
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\hbox to 1.75in{\enskip\hfil#\hfil}&
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\vrule#\cr
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\noalign{\hrule}
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&\bf Data Type &&\bf Alignment Requirement&\cr\noalign{\hrule}
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&byte&&1&\cr\noalign{\hrule}
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&half-word&&2&\cr\noalign{\hrule}
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&word&&4&\cr\noalign{\hrule}
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&doubleword&&8&\cr\noalign{\hrule}
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}}\hfil}
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@end tex
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@end ifset
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@ifset use-html
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@html
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<CENTER>
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<TABLE COLS=2 WIDTH="60%" BORDER=2>
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<TR><TD ALIGN=center><STRONG>Data Type</STRONG></TD>
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<TD ALIGN=center><STRONG>Alignment Requirement</STRONG></TD></TR>
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<TR><TD ALIGN=center>byte</TD>
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<TD ALIGN=center>1</TD></TR>
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<TR><TD ALIGN=center>half-word</TD>
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<TD ALIGN=center>2</TD></TR>
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<TR><TD ALIGN=center>word</TD>
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<TD ALIGN=center>4</TD></TR>
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<TR><TD ALIGN=center>doubleword</TD>
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<TD ALIGN=center>8</TD></TR>
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</TABLE>
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</CENTER>
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@end html
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@end ifset
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Doubleword load and store operations must use a pair
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of registers as their source or destination. This pair of
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registers must be an adjacent pair of registers with the first
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of the pair being even numbered. For example, a valid
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destination for a doubleword load might be input registers 0 and
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1 (i0 and i1). The pair i1 and i2 would be invalid. [NOTE:
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Some assemblers for the SPARC do not generate an error if an odd
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numbered register is specified as the beginning register of the
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pair. In this case, the assembler assumes that what the
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programmer meant was to use the even-odd pair which ends at the
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specified register. This may or may not have been a correct
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assumption.]
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RTEMS does not support any SPARC Memory Management
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Units, therefore, virtual memory or segmentation systems
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involving the SPARC are not supported.
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