forked from Imagelibrary/rtems
186 lines
6.3 KiB
C
186 lines
6.3 KiB
C
/**
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* @file tms570_tcram_tests.c
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*
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* @ingroup tms570
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*
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* @brief TCRAM selftest function.
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*/
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/*
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* Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
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*
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* Czech Technical University in Prague
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* Zikova 1903/4
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* 166 36 Praha 6
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* Czech Republic
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*
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* Algorithms are based on Ti manuals and Ti HalCoGen generated
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* code available under following copyright.
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*/
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/*
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* Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <stdint.h>
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#include <bsp/tms570.h>
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#include <bsp/tms570_selftest.h>
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#include <bsp/tms570_hwinit.h>
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#define tcramA1bitError (*(volatile uint32_t *)(0x08400000U))
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#define tcramA2bitError (*(volatile uint32_t *)(0x08400010U))
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#define tcramB1bitError (*(volatile uint32_t *)(0x08400008U))
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#define tcramB2bitError (*(volatile uint32_t *)(0x08400018U))
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#define tcramA1bit (*(volatile uint64_t *)(0x08000000U))
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#define tcramA2bit (*(volatile uint64_t *)(0x08000010U))
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#define tcramB1bit (*(volatile uint64_t *)(0x08000008U))
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#define tcramB2bit (*(volatile uint64_t *)(0x08000018U))
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/**
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* @brief Check TCRAM ECC error detection logic (HCG:checkRAMECC)
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*
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* This function checks TCRAM ECC error detection and correction logic.
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* The function does not return in case of TCRAM error.
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* It calls bsp_selftest_fail_notification() instead.
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*
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*/
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/* SourceId : SELFTEST_SourceId_034 */
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/* DesignId : SELFTEST_DesignId_019 */
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/* Requirements : HL_SR408 */
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void tms570_check_tcram_ecc( void )
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{
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volatile uint64_t ramread;
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volatile uint32_t regread;
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uint32_t tcram1ErrStat, tcram2ErrStat = 0U;
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uint64_t tcramA1_bk = tcramA1bit;
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uint64_t tcramB1_bk = tcramB1bit;
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uint64_t tcramA2_bk = tcramA2bit;
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uint64_t tcramB2_bk = tcramB2bit;
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/* Clear RAMOCUUR before setting RAMTHRESHOLD register */
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TMS570_TCRAM1.RAMOCCUR = 0U;
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TMS570_TCRAM2.RAMOCCUR = 0U;
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/* Set Single-bit Error Threshold Count as 1 */
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TMS570_TCRAM1.RAMTHRESHOLD = 1U;
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TMS570_TCRAM2.RAMTHRESHOLD = 1U;
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/* Enable single bit error generation */
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TMS570_TCRAM1.RAMINTCTRL = 1U;
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TMS570_TCRAM2.RAMINTCTRL = 1U;
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/* Enable writes to ECC RAM, enable ECC error response */
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TMS570_TCRAM1.RAMCTRL = 0x0005010AU;
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TMS570_TCRAM2.RAMCTRL = 0x0005010AU;
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/* Force a single bit error in both the banks */
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_coreDisableRamEcc_();
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tcramA1bitError ^= 1U;
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tcramB1bitError ^= 1U;
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_coreEnableRamEcc_();
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/* Read the corrupted data to generate single bit error */
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ramread = tcramA1bit;
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ramread = tcramB1bit;
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(void)ramread;
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/* Check for error status */
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tcram1ErrStat = TMS570_TCRAM1.RAMERRSTATUS & 0x1U;
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tcram2ErrStat = TMS570_TCRAM2.RAMERRSTATUS & 0x1U;
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/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "LDRA Tool issue" */
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/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "LDRA Tool issue" */
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if ((tcram1ErrStat == 0U) || (tcram2ErrStat == 0U)) {
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/* TCRAM module does not reflect 1-bit error reported by CPU */
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bsp_selftest_fail_notification(CHECKRAMECC_FAIL1);
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} else {
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if (!tms570_esm_channel_sr_get(1, 26) || !tms570_esm_channel_sr_get(1, 28)) {
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/* TCRAM 1-bit error not flagged in ESM */
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bsp_selftest_fail_notification(CHECKRAMECC_FAIL2);
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} else {
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/* Clear single bit error flag in TCRAM module */
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TMS570_TCRAM1.RAMERRSTATUS = 0x1U;
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TMS570_TCRAM2.RAMERRSTATUS = 0x1U;
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/* Clear ESM status */
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tms570_esm_channel_sr_clear(1, 26);
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tms570_esm_channel_sr_clear(1, 28);
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}
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}
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#if 0
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/*
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* This test sequence requires that data abort exception
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* handler checks for ECC test write enable in RAMCTR (bit 8)
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* and if the access abort is intended then it should clear
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* error status TCRAM status register and checks and clears
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* ESM group3 uncorrectable TCRAM error channels.
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*
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* More modifications in BSP and RTEMS ARM support are
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* required to make this code work.
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*/
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/* Force a double bit error in both the banks */
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_coreDisableRamEcc_();
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tcramA2bitError ^= 3U;
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tcramB2bitError ^= 3U;
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_coreEnableRamEcc_();
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/* Read the corrupted data to generate double bit error */
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ramread = tcramA2bit;
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ramread = tcramB2bit;
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/* read from location with 2-bit ECC error this will cause a data abort to be generated */
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/* See HalCoGen support src/sys/asm/dabort.asm */
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/* _ARMV4_Exception_data_abort_default has to include solution for this special case for RTEMS */
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#endif
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regread = TMS570_TCRAM1.RAMUERRADDR;
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regread = TMS570_TCRAM2.RAMUERRADDR;
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(void)regread;
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/* disable writes to ECC RAM */
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TMS570_TCRAM1.RAMCTRL = 0x0005000AU;
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TMS570_TCRAM2.RAMCTRL = 0x0005000AU;
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/* Compute correct ECC */
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tcramA1bit = tcramA1_bk;
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tcramB1bit = tcramB1_bk;
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tcramA2bit = tcramA2_bk;
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tcramB2bit = tcramB2_bk;
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}
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