forked from Imagelibrary/rtems
599 lines
19 KiB
C
599 lines
19 KiB
C
/**
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* @file tms570_selftest.c
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*
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* @ingroup tms570
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*
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* @brief TMS570 selftest support functions implementation.
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*/
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/*
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* Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <stdint.h>
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#include <stdbool.h>
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#include <stddef.h>
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#include <bsp/tms570.h>
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#include <bsp/tms570_selftest.h>
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#include <bsp/tms570_hwinit.h>
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/**
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* @brief Checks to see if the EFUSE Stuck at zero test is completed successfully (HCG:efcStuckZeroTest).
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/
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* @return 1 if EFUSE Stuck at zero test completed, otherwise 0.
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*
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* Checks to see if the EFUSE Stuck at zero test is completed successfully.
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*/
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/* SourceId : SELFTEST_SourceId_012 */
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/* DesignId : SELFTEST_DesignId_014 */
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/* Requirements : HL_SR402 */
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bool tms570_efc_stuck_zero( void )
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{
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uint32_t esm_estatus4, esm_estatus1;
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bool result = false;
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uint32_t output_enable = TMS570_EFUSE_EFCBOUND_Self_Test_Error_OE |
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TMS570_EFUSE_EFCBOUND_Single_Bit_Error_OE |
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TMS570_EFUSE_EFCBOUND_Instruction_Error_OE |
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TMS570_EFUSE_EFCBOUND_Autoload_Error_OE;
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uint32_t error_checks = TMS570_EFUSE_EFCBOUND_EFC_Single_Bit_Error |
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TMS570_EFUSE_EFCBOUND_EFC_Instruction_Error |
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TMS570_EFUSE_EFCBOUND_EFC_Autoload_Error |
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TMS570_EFUSE_EFCBOUND_EFC_Self_Test_Error;
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/* configure the output enable for auto load error , instruction info,
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instruction error, and self test error using boundary register
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and drive values one across all the errors */
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TMS570_EFUSE.EFCBOUND = output_enable | error_checks;
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/* Read from the pin register. This register holds the current values
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of above errors. This value should be 0x5c00.If not at least one of
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the above errors is stuck at 0. */
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if ( ( TMS570_EFUSE.EFCPINS & 0x5C00U ) == 0x5C00U ) {
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esm_estatus4 = TMS570_ESM.SR4;
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esm_estatus1 = TMS570_ESM.SR[ 2U ];
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/* check if the ESM group1 channel 41 is set and group3 channel 1 is set */
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if ( ( ( esm_estatus4 & 0x200U ) == 0x200U ) &&
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( ( esm_estatus1 & 0x2U ) == 0x2U ) ) {
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/* stuck-at-zero test passed */
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result = true;
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}
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}
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/* put the pins back low */
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TMS570_EFUSE.EFCBOUND = output_enable;
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/* clear group1 flag */
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TMS570_ESM.SR4 = 0x200U;
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/* clear group3 flag */
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TMS570_ESM.SR[ 2U ] = 0x2U;
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/* The nERROR pin will become inactive once the LTC counter expires */
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TMS570_ESM.EKR = 0x5U;
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return result;
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}
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/**
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* @brief EFUSE module self check Driver (HCG:efcSelfTest)
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*
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* This function self checks the EFSUE module.
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*/
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/* SourceId : SELFTEST_SourceId_013 */
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/* DesignId : SELFTEST_DesignId_013 */
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/* Requirements : HL_SR402 */
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void tms570_efc_self_test( void )
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{
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/* configure self-test cycles */
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TMS570_EFUSE.EFC_ST_CY = 0x258U;
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/* configure self-test signature */
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TMS570_EFUSE.EFC_ST_SIG = 0x5362F97FU;
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/* configure boundary register to start ECC self-test */
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TMS570_EFUSE.EFCBOUND = 0x00002000 |
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TMS570_EFUSE_EFCBOUND_Input_Enable( 0xF );
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}
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/**
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* @brief EFUSE module self check Driver (HCG:checkefcSelfTest)
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*
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* @return Returns TRUE if EFC Selftest was a PASS, else FALSE
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*
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* This function returns the status of efcSelfTest.
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* Note: This function can be called only after calling efcSelfTest
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*/
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/* SourceId : SELFTEST_SourceId_014 */
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/* DesignId : SELFTEST_DesignId_015 */
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/* Requirements : HL_SR403 */
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bool tms570_efc_check_self_test( void )
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{
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bool result = false;
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uint32_t efc_pins, efc_error;
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uint32_t esmCh40Stat, esmCh41Stat = 0U;
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/* wait until EFC self-test is done */
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/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
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while ( ( TMS570_EFUSE.EFCPINS & TMS570_EFUSE_EFCPINS_EFC_Selftest_Done ) ==
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0U ) {
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} /* Wait */
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/* check if EFC self-test error occurred */
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efc_pins = TMS570_EFUSE.EFCPINS;
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efc_error = TMS570_EFUSE.EFC_ERR_STAT;
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if ( ( ( efc_pins & TMS570_EFUSE_EFCPINS_EFC_Selftest_Error ) == 0U ) &&
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( ( efc_error & 0x1FU ) == 0U ) ) {
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/* check if EFC self-test error is set */
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esmCh40Stat = TMS570_ESM.SR4 & 0x100U;
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esmCh41Stat = TMS570_ESM.SR4 & 0x200U;
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if ( ( esmCh40Stat == 0U ) && ( esmCh41Stat == 0U ) ) {
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result = true;
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}
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}
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return result;
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}
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/**
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* @brief EFUSE module self check Driver (HCG:efcCheck)
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* @return Returns 0 if no error was detected during autoload and Stuck At Zero Test passed
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* 1 if no error was detected during autoload but Stuck At Zero Test failed
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* 2 if there was a single-bit error detected during autoload
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* 3 if some other error occurred during autoload
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*
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* This function self checks the EFUSE module.
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*/
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/* SourceId : SELFTEST_SourceId_011 */
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/* DesignId : SELFTEST_DesignId_012 */
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/* Requirements : HL_SR402 */
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uint32_t tms570_efc_check( void )
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{
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uint32_t efc_status = 0U;
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uint32_t status;
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/* read the EFC Error Status Register */
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efc_status = TMS570_EFUSE.EFC_ERR_STAT;
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if ( efc_status == 0x0U ) {
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/* run stuck-at-zero test and check if it passed */
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if ( tms570_efc_stuck_zero() == true ) {
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/* start EFC ECC logic self-test */
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tms570_efc_self_test();
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status = 0U;
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} else {
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/* EFC output is stuck-at-zero, device operation unreliable */
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bsp_selftest_fail_notification( EFCCHECK_FAIL1 );
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status = 1U;
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}
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}
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/* EFC Error Register is not zero */
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else {
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/* one-bit error detected during autoload */
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if ( efc_status == 0x15U ) {
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/* start EFC ECC logic self-test */
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tms570_efc_self_test();
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status = 2U;
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} else {
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/* Some other EFC error was detected */
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bsp_selftest_fail_notification( EFCCHECK_FAIL1 );
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status = 3U;
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}
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}
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return status;
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}
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/**
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* @brief PBIST self test Driver (HCG:pbistSelfCheck)
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*
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* This function is called to perform PBIST self test.
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*/
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/* SourceId : SELFTEST_SourceId_005 */
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/* DesignId : SELFTEST_DesignId_005 */
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/* Requirements : HL_SR399 */
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void tms570_pbist_self_check( void )
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{
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volatile uint32_t i = 0U;
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uint32_t PBIST_wait_done_loop = 0U;
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/* Run a diagnostic check on the memory self-test controller */
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/* First set up the PBIST ROM clock as this clock frequency is limited to 90MHz */
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/* Disable PBIST clocks and ROM clock */
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TMS570_PBIST.PACT = 0x0U;
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/* PBIST ROM clock frequency = HCLK frequency /2 */
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/* Disable memory self controller */
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TMS570_SYS1.MSTGCR = 0x00000105U;
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/* Disable Memory Initialization controller */
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TMS570_SYS1.MINITGCR = 0x5U;
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/* Enable memory self controller */
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TMS570_SYS1.MSTGCR = 0x0000010AU;
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/* Clear PBIST Done */
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TMS570_SYS1.MSTCGSTAT = 0x1U;
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/* Enable PBIST controller */
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TMS570_SYS1.MSIENA = 0x1U;
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/* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */
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/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
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/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
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for ( i = 0U; i < ( 32U + ( 32U * 1U ) ); i++ ) { /* Wait */
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}
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/* Enable PBIST clocks and ROM clock */
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TMS570_PBIST.PACT = 0x3U;
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/* CPU control of PBIST */
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TMS570_PBIST.DLR = 0x10U;
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/* Custom always fail algo, this will not use the ROM and just set a fail */
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TMS570_PBIST.RAMT = 0x00002000U;
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*(volatile uint32_t *) 0xFFFFE400U = 0x4C000001U;
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*(volatile uint32_t *) 0xFFFFE440U = 0x00000075U;
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*(volatile uint32_t *) 0xFFFFE404U = 0x4C000002U;
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*(volatile uint32_t *) 0xFFFFE444U = 0x00000075U;
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*(volatile uint32_t *) 0xFFFFE408U = 0x4C000003U;
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*(volatile uint32_t *) 0xFFFFE448U = 0x00000075U;
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*(volatile uint32_t *) 0xFFFFE40CU = 0x4C000004U;
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*(volatile uint32_t *) 0xFFFFE44CU = 0x00000075U;
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*(volatile uint32_t *) 0xFFFFE410U = 0x4C000005U;
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*(volatile uint32_t *) 0xFFFFE450U = 0x00000075U;
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*(volatile uint32_t *) 0xFFFFE414U = 0x4C000006U;
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*(volatile uint32_t *) 0xFFFFE454U = 0x00000075U;
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*(volatile uint32_t *) 0xFFFFE418U = 0x00000000U;
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*(volatile uint32_t *) 0xFFFFE458U = 0x00000001U;
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/* PBIST_RUN */
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( &TMS570_PBIST.DLR )[ 2 ] = 1;
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/* wait until memory self-test done is indicated */
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/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
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while ( ( TMS570_SYS1.MSTCGSTAT & 0x1U ) != 0x1U )
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PBIST_wait_done_loop++;
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/* Wait */
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/* Check for the failure */
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if ( ( TMS570_PBIST.FSRF0 & 0x1U ) != 0x1U ) {
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/* No failure was indicated even if the always fail algorithm was run*/
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bsp_selftest_fail_notification( PBISTSELFCHECK_FAIL1 );
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} else {
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/* Check that the algorithm executed in the expected amount of time. */
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/* This time is dependent on the ROMCLKDIV selected above */
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if ( PBIST_wait_done_loop >= 2U ) {
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bsp_selftest_fail_notification( PBISTSELFCHECK_FAIL2 );
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}
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/* Disable PBIST clocks and ROM clock */
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TMS570_PBIST.PACT = 0x0U;
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/* Disable PBIST */
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TMS570_SYS1.MSTGCR &= 0xFFFFFFF0U;
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TMS570_SYS1.MSTGCR |= 0x5U;
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}
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}
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/**
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* @brief CPU self test Driver (HCG:pbistRun)
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* @param[in] raminfoL - Select the list of RAM to be tested.
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* @param[in] algomask - Select the list of Algorithm to be run.
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*
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* This function performs Memory Built-in Self test using PBIST module.
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*/
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/* SourceId : SELFTEST_SourceId_006 */
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/* DesignId : SELFTEST_DesignId_006 */
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/* Requirements : HL_SR400 */
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void tms570_pbist_run(
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uint32_t raminfoL,
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uint32_t algomask
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)
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{
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volatile uint32_t i = 0U;
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/* PBIST ROM clock frequency = HCLK frequency /2 */
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/* Disable memory self controller */
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TMS570_SYS1.MSTGCR = 0x00000105U;
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/* Disable Memory Initialization controller */
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TMS570_SYS1.MINITGCR = 0x5U;
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/* Enable PBIST controller */
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TMS570_SYS1.MSIENA = 0x1U;
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/* Enable memory self controller */
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TMS570_SYS1.MSTGCR = 0x0000010AU;
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/* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */
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/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
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/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
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for ( i = 0U; i < ( 32U + ( 32U * 1U ) ); i++ ) { /* Wait */
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}
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/* Enable PBIST clocks and ROM clock */
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TMS570_PBIST.PACT = 0x3U;
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/* Select all algorithms to be tested */
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TMS570_PBIST.ALGO = algomask;
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/* Select RAM groups */
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TMS570_PBIST.RINFOL = raminfoL;
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/* Select all RAM groups */
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TMS570_PBIST.RINFOUL = 0x00000000U;
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/* ROM contents will not override RINFOx settings */
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TMS570_PBIST.OVER = 0x0U;
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/* Algorithm code is loaded from ROM */
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TMS570_PBIST.ROM = 0x3U;
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/* Start PBIST */
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TMS570_PBIST.DLR = 0x14U;
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}
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/**
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* @brief Routine to stop PBIST test enabled (HCG:pbistStop)
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*
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* This function is called to stop PBIST after test is performed.
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*/
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/* SourceId : SELFTEST_SourceId_007 */
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/* DesignId : SELFTEST_DesignId_007 */
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/* Requirements : HL_SR523 */
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void tms570_pbist_stop( void )
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{
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/* disable pbist clocks and ROM clock */
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TMS570_PBIST.PACT = 0x0U;
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TMS570_SYS1.MSTGCR &= 0xFFFFFFF0U;
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TMS570_SYS1.MSTGCR |= 0x5U;
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}
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/**
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* @brief Checks to see if the PBIST test is completed (HCG:pbistIsTestCompleted)
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* @return 1 if PBIST test completed, otherwise 0.
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*
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* Checks to see if the PBIST test is completed.
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*/
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/* SourceId : SELFTEST_SourceId_008 */
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/* DesignId : SELFTEST_DesignId_008 */
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/* Requirements : HL_SR401 */
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bool tms570_pbist_is_test_completed( void )
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{
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return ( ( TMS570_SYS1.MSTCGSTAT & 0x1U ) != 0U );
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}
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/**
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* @brief Checks to see if the PBIST test is completed successfully (HCG:pbistIsTestPassed)
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* @return 1 if PBIST test passed, otherwise 0.
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*
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* Checks to see if the PBIST test is completed successfully.
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*/
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/* SourceId : SELFTEST_SourceId_009 */
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/* DesignId : SELFTEST_DesignId_009 */
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/* Requirements : HL_SR401 */
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bool tms570_pbist_is_test_passed( void )
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{
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bool status;
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if ( TMS570_PBIST.FSRF0 == 0U ) {
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status = true;
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} else {
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status = false;
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}
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return status;
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}
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/**
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* @brief Checks to see if the PBIST Port test is completed successfully (HCG:pbistPortTestStatus)
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* @param[in] port - Select the port to get the status.
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* @return 1 if PBIST Port test completed successfully, otherwise 0.
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*
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* Checks to see if the selected PBIST Port test is completed successfully.
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*/
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/* SourceId : SELFTEST_SourceId_010 */
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/* DesignId : SELFTEST_DesignId_010 */
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/* Requirements : HL_SR401 */
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bool tms570_pbist_port_test_status( uint32_t port )
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{
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bool status;
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if ( port == (uint32_t) PBIST_PORT0 ) {
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status = ( TMS570_PBIST.FSRF0 == 0U );
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} else {
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/* Invalid Input */
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status = false;
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}
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return status;
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}
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/**
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* @brief Reaction to PBIST failure (HCG:pbistFail)
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*
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* @return Void.
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*/
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/* SourceId : SELFTEST_SourceId_042 */
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/* DesignId : SELFTEST_DesignId_011 */
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/* Requirements : HL_SR401 */
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void tms570_pbist_fail( void )
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{
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uint32_t PBIST_RAMT, PBIST_FSRA0, PBIST_FSRDL0;
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/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
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PBIST_RAMT = TMS570_PBIST.RAMT;
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PBIST_FSRA0 = TMS570_PBIST.FSRA0;
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PBIST_FSRDL0 = TMS570_PBIST.FSRDL0;
|
|
|
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if ( tms570_pbist_port_test_status( (uint32_t) PBIST_PORT0 ) != true ) {
|
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uint32_t groupSelect = ( PBIST_RAMT & 0xFF000000U ) >> 24U;
|
|
uint32_t dataSelect = ( PBIST_RAMT & 0x00FF0000U ) >> 16U;
|
|
uint32_t address = PBIST_FSRA0;
|
|
uint32_t data = PBIST_FSRDL0;
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tms570_memory_port0_fail_notification( groupSelect,
|
|
dataSelect,
|
|
address,
|
|
data );
|
|
} else {
|
|
/*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
|
|
/*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
|
|
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
|
|
for (;; ) {
|
|
} /* Wait */
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Memory Initialization Driver (HCG:memoryInit)
|
|
*
|
|
* This function is called to perform Memory initialization of selected RAM's.
|
|
*/
|
|
/* SourceId : SELFTEST_SourceId_002 */
|
|
/* DesignId : SELFTEST_DesignId_004 */
|
|
/* Requirements : HL_SR396 */
|
|
void tms570_memory_init( uint32_t ram )
|
|
{
|
|
/* Enable Memory Hardware Initialization */
|
|
TMS570_SYS1.MINITGCR = 0xAU;
|
|
|
|
/* Enable Memory Hardware Initialization for selected RAM's */
|
|
TMS570_SYS1.MSIENA = ram;
|
|
|
|
/* Wait until Memory Hardware Initialization complete */
|
|
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
|
|
while ( ( TMS570_SYS1.MSTCGSTAT & 0x00000100U ) != 0x00000100U ) {
|
|
} /* Wait */
|
|
|
|
/* Disable Memory Hardware Initialization */
|
|
TMS570_SYS1.MINITGCR = 0x5U;
|
|
}
|
|
|
|
volatile uint32_t *const
|
|
tms570_esm_group_channel_to_sr_table[ 4 ][ 2 ] = {
|
|
{ NULL, NULL },
|
|
{ &TMS570_ESM.SR[ 0 ], &TMS570_ESM.SR4 },
|
|
{ &TMS570_ESM.SR[ 1 ], NULL },
|
|
{ &TMS570_ESM.SR[ 2 ], NULL },
|
|
};
|
|
|
|
/**
|
|
* @brief Routine to clear specified error channel signalling bit
|
|
* @param[in] grp - ESM error channels group
|
|
* @param[in] chan - ESM error channel number inside specified group
|
|
*/
|
|
void tms570_esm_channel_sr_clear(
|
|
unsigned grp,
|
|
unsigned chan
|
|
)
|
|
{
|
|
volatile uint32_t *sr_reg;
|
|
|
|
sr_reg = tms570_esm_group_channel_to_sr_table[ grp ][ chan >> 5 ];
|
|
|
|
if ( sr_reg != NULL )
|
|
*sr_reg = 1 << (chan & 0x1f);
|
|
}
|
|
|
|
/** tms570_esm_channel_sr_get
|
|
* @brief Routine to test is specified error channel is signalling error
|
|
* @param[in] grp - ESM error channels group
|
|
* @param[in] chan - ESM error channel number inside specified group
|
|
*/
|
|
int tms570_esm_channel_sr_get(
|
|
unsigned grp,
|
|
unsigned chan
|
|
)
|
|
{
|
|
volatile uint32_t *sr_reg;
|
|
|
|
sr_reg = tms570_esm_group_channel_to_sr_table[ grp ][ chan >> 5 ];
|
|
|
|
if ( sr_reg != NULL )
|
|
return *sr_reg & ( 1 << ( chan & 0x1f ) );
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* @brief Enable peripheral RAM parity (HCG:enableParity)
|
|
*
|
|
* This function enables RAM parity for all peripherals for which RAM parity check is enabled.
|
|
* This function is called before memoryInit in the startup
|
|
*
|
|
*/
|
|
void tms570_enable_parity( void )
|
|
{
|
|
TMS570_DMA.DMAPCR = 0xAU; /* Enable DMA RAM parity */
|
|
TMS570_VIM.PARCTL = 0xAU; /* Enable VIM RAM parity */
|
|
TMS570_DCAN1.CTL = ((uint32_t)0xAU << 10U) | 1U; /* Enable CAN1 RAM parity */
|
|
TMS570_DCAN2.CTL = ((uint32_t)0xAU << 10U) | 1U; /* Enable CAN2 RAM parity */
|
|
TMS570_DCAN3.CTL = ((uint32_t)0xAU << 10U) | 1U; /* Enable CAN3 RAM parity */
|
|
TMS570_ADC1.PARCR = 0xAU; /* Enable ADC1 RAM parity */
|
|
TMS570_ADC2.PARCR = 0xAU; /* Enable ADC2 RAM parity */
|
|
TMS570_NHET1.PCR = 0xAU; /* Enable HET1 RAM parity */
|
|
TMS570_HTU1.PCR = 0xAU; /* Enable HTU1 RAM parity */
|
|
TMS570_NHET2.PCR = 0xAU; /* Enable HET2 RAM parity */
|
|
TMS570_HTU2.PCR = 0xAU; /* Enable HTU2 RAM parity */
|
|
}
|
|
|
|
/**
|
|
* @brief Disable peripheral RAM parity (HCG:disableParity)
|
|
*
|
|
* This function disables RAM parity for all peripherals for which RAM parity check is enabled.
|
|
* This function is called after memoryInit in the startup
|
|
*
|
|
*/
|
|
void tms570_disable_parity( void )
|
|
{
|
|
TMS570_DMA.DMAPCR = 0x5U; /* Disable DMA RAM parity */
|
|
TMS570_VIM.PARCTL = 0x5U; /* Disable VIM RAM parity */
|
|
TMS570_DCAN1.CTL = ((uint32_t)0x5U << 10U) | 1U; /* Disable CAN1 RAM parity */
|
|
TMS570_DCAN2.CTL = ((uint32_t)0x5U << 10U) | 1U; /* Disable CAN2 RAM parity */
|
|
TMS570_DCAN3.CTL = ((uint32_t)0x5U << 10U) | 1U; /* Disable CAN3 RAM parity */
|
|
TMS570_ADC1.PARCR = 0x5U; /* Disable ADC1 RAM parity */
|
|
TMS570_ADC2.PARCR = 0x5U; /* Disable ADC2 RAM parity */
|
|
TMS570_NHET1.PCR = 0x5U; /* Disable HET1 RAM parity */
|
|
TMS570_HTU1.PCR = 0x5U; /* Disable HTU1 RAM parity */
|
|
TMS570_NHET2.PCR = 0x5U; /* Disable HET2 RAM parity */
|
|
TMS570_HTU2.PCR = 0x5U; /* Disable HTU2 RAM parity */
|
|
}
|