forked from Imagelibrary/rtems
50539ba881
This support code is necessary for many Xilinx-provided bare metal device drivers supported on ARM, AArch64, and MicroBlaze platforms. Support for all of these architectures is kept under bsps/include due to multiple architecture variants being supported which requires complex logic in the build system. The imported files are and should be able to remain unmodified. Import information is kept in bsps/shared/xil/VERSION.
733 lines
20 KiB
C
733 lines
20 KiB
C
/******************************************************************************
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* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
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* SPDX-License-Identifier: MIT
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xil_cache.c
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*
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* Contains required functions for the ARM cache functionality.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 5.0 pkp 05/29/14 First release
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* 5.5 pkp 04/15/16 Updated the Xil_DCacheInvalidate,
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* Xil_DCacheInvalidateLine and Xil_DCacheInvalidateRange
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* functions description for proper explanation
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* 6.2 pkp 01/22/17 Added support for EL1 non-secure
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* 6.2 asa 01/31/17 The existing Xil_DCacheDisable API first flushes the
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* D caches and then disables it. The problem with that is,
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* potentially there will be a small window after the cache
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* flush operation and before the we disable D caches where
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* we might have valid data in cache lines. In such a
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* scenario disabling the D cache can lead to unknown behavior.
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* The ideal solution to this is to use assembly code for
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* the complete API and avoid any memory accesses. But with
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* that we will end up having a huge amount on assembly code
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* which is not maintainable. Changes are done to use a mix
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* of assembly and C code. All local variables are put in
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* registers. Also function calls are avoided in the API to
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* avoid using stack memory.
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* These changes fix CR#966220.
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* 6.2 mus 02/13/17 The new api Xil_ConfigureL1Prefetch is added to disable pre-fetching/configure
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* the maximum number of outstanding data prefetches allowed in
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* L1 cache system.It fixes CR#967864.
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* 6.6 mus 02/27/18 Updated Xil_DCacheInvalidateRange and
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* Xil_ICacheInvalidateRange APIs to change the data type of
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* "cacheline" variable as "INTPTR", This change has been done
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* to avoid the truncation of upper DDR addresses to 32 bit.It
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* fixes CR#995581.
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* 6.6 mus 03/15/18 By default CPUACTLR_EL1 is accessible only from EL3, it
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* results into abort if accessed from EL1 non secure privilege
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* level. Updated Xil_ConfigureL1Prefetch function to access
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* CPUACTLR_EL1 only for EL3.
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* 6.8 mn 08/01/18 Optimize the Xil_DCacheInvalidateRange() function to remove
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* redundant operations
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* 6.8 asa 09/15/18 Fix bug in the Xil_DCacheInvalidateRange API introduced while
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* making optimizations in the previous patch. This change fixes
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* CR-1008926.
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* 7.0 mus 10/12/18 Updated Xil_DCacheInvalidateLine and Xil_DCacheInvalidateRange
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* APIs to replace IVAC instruction with CIVAC. So that, these
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* APIs will always do flush + invalidate in case of Cortexa53 as
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* well as Cortexa72 processor.
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* 7.1 mus 09/17/19 Xil_DCacheFlushRange and Xil_DCacheInvalidateRange are executing
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* same functionality (clean + validate). Removed
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* Xil_DCacheFlushRange function implementation and defined it as
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* macro. Xil_DCacheFlushRange macro points to the
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* Xil_DCacheInvalidateRange API to avoid code duplication.
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*
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* </pre>
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include "xil_cache.h"
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#include "xil_io.h"
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#include "xpseudo_asm.h"
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#include "xparameters.h"
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#include "xreg_cortexa53.h"
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#include "xil_exception.h"
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#include "bspconfig.h"
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/************************** Function Prototypes ******************************/
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/************************** Variable Definitions *****************************/
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#define IRQ_FIQ_MASK 0xC0U /* Mask IRQ and FIQ interrupts in cpsr */
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/****************************************************************************/
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/**
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* @brief Enable the Data cache.
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*
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* @return None.
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*
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****************************************************************************/
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void Xil_DCacheEnable(void)
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{
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u32 CtrlReg;
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if (EL3 == 1) {
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CtrlReg = mfcp(SCTLR_EL3);
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} else if (EL1_NONSECURE == 1) {
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CtrlReg = mfcp(SCTLR_EL1);
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} else {
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CtrlReg = 0U;
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}
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/* enable caches only if they are disabled */
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if((CtrlReg & XREG_CONTROL_DCACHE_BIT) == 0X00000000U){
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/* invalidate the Data cache */
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Xil_DCacheInvalidate();
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CtrlReg |= XREG_CONTROL_DCACHE_BIT;
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if (EL3 == 1) {
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/* enable the Data cache for el3*/
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mtcp(SCTLR_EL3,CtrlReg);
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} else if (EL1_NONSECURE == 1) {
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/* enable the Data cache for el1*/
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mtcp(SCTLR_EL1,CtrlReg);
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}
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}
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}
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/****************************************************************************/
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/**
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* @brief Disable the Data cache.
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*
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* @return None.
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*
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****************************************************************************/
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void Xil_DCacheDisable(void)
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{
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register u32 CsidReg;
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register u32 C7Reg;
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register u32 LineSize;
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register u32 NumWays;
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register u32 Way;
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register u32 WayIndex;
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register u32 WayAdjust;
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register u32 Set;
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register u32 SetIndex;
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register u32 NumSet;
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register u32 CacheLevel;
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dsb();
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asm(
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"mov x0, #0\n\t"
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#if EL3==1
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"mrs x0, sctlr_el3 \n\t"
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"and w0, w0, #0xfffffffb\n\t"
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"msr sctlr_el3, x0\n\t"
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#elif EL1_NONSECURE==1
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"mrs x0, sctlr_el1 \n\t"
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"and w0, w0, #0xfffffffb\n\t"
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"msr sctlr_el1, x0\n\t"
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#endif
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"dsb sy\n\t"
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);
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/* Number of level of cache*/
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CacheLevel = 0U;
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/* Select cache level 0 and D cache in CSSR */
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mtcp(CSSELR_EL1,CacheLevel);
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isb();
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CsidReg = mfcp(CCSIDR_EL1);
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/* Get the cacheline size, way size, index size from csidr */
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LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
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/* Number of Ways */
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NumWays = (CsidReg & 0x00001FFFU) >> 3U;
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NumWays += 0x00000001U;
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/*Number of Set*/
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NumSet = (CsidReg >> 13U) & 0x00007FFFU;
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NumSet += 0x00000001U;
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WayAdjust = clz(NumWays) - (u32)0x0000001FU;
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Way = 0U;
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Set = 0U;
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/* Flush all the cachelines */
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for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
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for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
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C7Reg = Way | Set | CacheLevel;
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mtcpdc(CISW,C7Reg);
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Set += (0x00000001U << LineSize);
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}
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Set = 0U;
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Way += (0x00000001U << WayAdjust);
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}
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/* Wait for Flush to complete */
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dsb();
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/* Select cache level 1 and D cache in CSSR */
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CacheLevel += (0x00000001U << 1U);
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mtcp(CSSELR_EL1,CacheLevel);
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isb();
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CsidReg = mfcp(CCSIDR_EL1);
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/* Get the cacheline size, way size, index size from csidr */
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LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
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/* Number of Ways */
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NumWays = (CsidReg & 0x00001FFFU) >> 3U;
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NumWays += 0x00000001U;
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/* Number of Sets */
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NumSet = (CsidReg >> 13U) & 0x00007FFFU;
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NumSet += 0x00000001U;
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WayAdjust=clz(NumWays) - (u32)0x0000001FU;
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Way = 0U;
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Set = 0U;
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/* Flush all the cachelines */
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for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
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for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
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C7Reg = Way | Set | CacheLevel;
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mtcpdc(CISW,C7Reg);
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Set += (0x00000001U << LineSize);
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}
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Set=0U;
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Way += (0x00000001U<<WayAdjust);
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}
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/* Wait for Flush to complete */
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dsb();
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asm(
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#if EL3==1
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"tlbi ALLE3\n\t"
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#elif EL1_NONSECURE==1
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"tlbi VMALLE1\n\t"
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#endif
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"dsb sy\r\n"
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"isb\n\t"
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);
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}
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/****************************************************************************/
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/**
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* @brief Invalidate the Data cache. The contents present in the cache are
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* cleaned and invalidated.
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*
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* @return None.
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*
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* @note In Cortex-A53, functionality to simply invalid the cachelines
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* is not present. Such operations are a problem for an environment
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* that supports virtualisation. It would allow one OS to invalidate
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* a line belonging to another OS. This could lead to the other OS
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* crashing because of the loss of essential data. Hence, such
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* operations are promoted to clean and invalidate which avoids such
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* corruption.
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*
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****************************************************************************/
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void Xil_DCacheInvalidate(void)
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{
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register u32 CsidReg, C7Reg;
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u32 LineSize, NumWays;
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u32 Way, WayIndex,WayAdjust, Set, SetIndex, NumSet, CacheLevel;
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u32 currmask;
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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/* Number of level of cache*/
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CacheLevel=0U;
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/* Select cache level 0 and D cache in CSSR */
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mtcp(CSSELR_EL1,CacheLevel);
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isb();
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CsidReg = mfcp(CCSIDR_EL1);
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/* Get the cacheline size, way size, index size from csidr */
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LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
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/* Number of Ways */
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NumWays = (CsidReg & 0x00001FFFU) >> 3U;
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NumWays += 0X00000001U;
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/*Number of Set*/
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NumSet = (CsidReg >> 13U) & 0x00007FFFU;
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NumSet += 0X00000001U;
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WayAdjust = clz(NumWays) - (u32)0x0000001FU;
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Way = 0U;
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Set = 0U;
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/* Invalidate all the cachelines */
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for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
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for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
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C7Reg = Way | Set | CacheLevel;
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mtcpdc(ISW,C7Reg);
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Set += (0x00000001U << LineSize);
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}
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Set = 0U;
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Way += (0x00000001U << WayAdjust);
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}
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/* Wait for invalidate to complete */
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dsb();
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/* Select cache level 1 and D cache in CSSR */
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CacheLevel += (0x00000001U<<1U) ;
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mtcp(CSSELR_EL1,CacheLevel);
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isb();
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CsidReg = mfcp(CCSIDR_EL1);
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/* Get the cacheline size, way size, index size from csidr */
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LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
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/* Number of Ways */
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NumWays = (CsidReg & 0x00001FFFU) >> 3U;
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NumWays += 0x00000001U;
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/* Number of Sets */
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NumSet = (CsidReg >> 13U) & 0x00007FFFU;
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NumSet += 0x00000001U;
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WayAdjust = clz(NumWays) - (u32)0x0000001FU;
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Way = 0U;
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Set = 0U;
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/* Invalidate all the cachelines */
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for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
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for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
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C7Reg = Way | Set | CacheLevel;
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mtcpdc(ISW,C7Reg);
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Set += (0x00000001U << LineSize);
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}
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Set = 0U;
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Way += (0x00000001U << WayAdjust);
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}
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/* Wait for invalidate to complete */
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dsb();
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mtcpsr(currmask);
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}
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/****************************************************************************/
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/**
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* @brief Invalidate a Data cache line. The cacheline is cleaned and
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* invalidated.
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*
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* @param adr: 64bit address of the data to be flushed.
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*
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* @return None.
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*
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* @note In Cortex-A53, functionality to simply invalid the cachelines
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* is not present. Such operations are a problem for an environment
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* that supports virtualisation. It would allow one OS to invalidate
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* a line belonging to another OS. This could lead to the other OS
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* crashing because of the loss of essential data. Hence, such
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* operations are promoted to clean and invalidate which avoids such
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* corruption.
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*
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****************************************************************************/
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void Xil_DCacheInvalidateLine(INTPTR adr)
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{
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u32 currmask;
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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/* Select cache level 0 and D cache in CSSR */
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mtcp(CSSELR_EL1,0x0);
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mtcpdc(CIVAC,(adr & (~0x3F)));
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/* Wait for invalidate to complete */
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dsb();
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/* Select cache level 1 and D cache in CSSR */
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mtcp(CSSELR_EL1,0x2);
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mtcpdc(IVAC,(adr & (~0x3F)));
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/* Wait for invalidate to complete */
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dsb();
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mtcpsr(currmask);
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}
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/****************************************************************************/
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/**
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* @brief Invalidate the Data cache for the given address range.
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* The cachelines present in the adderss range are cleaned and
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* invalidated
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*
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* @param adr: 64bit start address of the range to be invalidated.
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* @param len: Length of the range to be invalidated in bytes.
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*
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* @return None.
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*
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* @note In Cortex-A53, functionality to simply invalid the cachelines
|
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* is not present. Such operations are a problem for an environment
|
|
* that supports virtualisation. It would allow one OS to invalidate
|
|
* a line belonging to another OS. This could lead to the other OS
|
|
* crashing because of the loss of essential data. Hence, such
|
|
* operations are promoted to clean and invalidate which avoids such
|
|
* corruption.
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*
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****************************************************************************/
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void Xil_DCacheInvalidateRange(INTPTR adr, INTPTR len)
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{
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const INTPTR cacheline = 64U;
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INTPTR end = adr + len;
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adr = adr & (~0x3F);
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u32 currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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if (len != 0U) {
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while (adr < end) {
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mtcpdc(CIVAC,adr);
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adr += cacheline;
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}
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}
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/* Wait for invalidate to complete */
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dsb();
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mtcpsr(currmask);
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}
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/****************************************************************************/
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/**
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* @brief Flush the Data cache.
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*
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* @return None.
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*
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****************************************************************************/
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void Xil_DCacheFlush(void)
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{
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register u32 CsidReg, C7Reg;
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u32 LineSize, NumWays;
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u32 Way, WayIndex,WayAdjust, Set, SetIndex, NumSet, CacheLevel;
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u32 currmask;
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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|
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/* Number of level of cache*/
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CacheLevel = 0U;
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/* Select cache level 0 and D cache in CSSR */
|
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mtcp(CSSELR_EL1,CacheLevel);
|
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isb();
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CsidReg = mfcp(CCSIDR_EL1);
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/* Get the cacheline size, way size, index size from csidr */
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LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
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/* Number of Ways */
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NumWays = (CsidReg & 0x00001FFFU) >> 3U;
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NumWays += 0x00000001U;
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/*Number of Set*/
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NumSet = (CsidReg >> 13U) & 0x00007FFFU;
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NumSet += 0x00000001U;
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WayAdjust = clz(NumWays) - (u32)0x0000001FU;
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Way = 0U;
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Set = 0U;
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/* Flush all the cachelines */
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for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
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for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
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C7Reg = Way | Set | CacheLevel;
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mtcpdc(CISW,C7Reg);
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Set += (0x00000001U << LineSize);
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}
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Set = 0U;
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Way += (0x00000001U << WayAdjust);
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}
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|
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/* Wait for Flush to complete */
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dsb();
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/* Select cache level 1 and D cache in CSSR */
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CacheLevel += (0x00000001U << 1U);
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mtcp(CSSELR_EL1,CacheLevel);
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isb();
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CsidReg = mfcp(CCSIDR_EL1);
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/* Get the cacheline size, way size, index size from csidr */
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LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
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/* Number of Ways */
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NumWays = (CsidReg & 0x00001FFFU) >> 3U;
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NumWays += 0x00000001U;
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/* Number of Sets */
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NumSet = (CsidReg >> 13U) & 0x00007FFFU;
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NumSet += 0x00000001U;
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WayAdjust=clz(NumWays) - (u32)0x0000001FU;
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Way = 0U;
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Set = 0U;
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/* Flush all the cachelines */
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for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
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for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
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C7Reg = Way | Set | CacheLevel;
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mtcpdc(CISW,C7Reg);
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Set += (0x00000001U << LineSize);
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}
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Set=0U;
|
|
Way += (0x00000001U<<WayAdjust);
|
|
}
|
|
/* Wait for Flush to complete */
|
|
dsb();
|
|
|
|
mtcpsr(currmask);
|
|
}
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* @brief Flush a Data cache line. If the byte specified by the address (adr)
|
|
* is cached by the Data cache, the cacheline containing that byte is
|
|
* invalidated. If the cacheline is modified (dirty), the entire
|
|
* contents of the cacheline are written to system memory before the
|
|
* line is invalidated.
|
|
*
|
|
* @param adr: 64bit address of the data to be flushed.
|
|
*
|
|
* @return None.
|
|
*
|
|
* @note The bottom 6 bits are set to 0, forced by architecture.
|
|
*
|
|
****************************************************************************/
|
|
void Xil_DCacheFlushLine(INTPTR adr)
|
|
{
|
|
u32 currmask;
|
|
currmask = mfcpsr();
|
|
mtcpsr(currmask | IRQ_FIQ_MASK);
|
|
/* Select cache level 0 and D cache in CSSR */
|
|
mtcp(CSSELR_EL1,0x0);
|
|
mtcpdc(CIVAC,(adr & (~0x3F)));
|
|
/* Wait for flush to complete */
|
|
dsb();
|
|
/* Select cache level 1 and D cache in CSSR */
|
|
mtcp(CSSELR_EL1,0x2);
|
|
mtcpdc(CIVAC,(adr & (~0x3F)));
|
|
/* Wait for flush to complete */
|
|
dsb();
|
|
mtcpsr(currmask);
|
|
}
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* @brief Enable the instruction cache.
|
|
*
|
|
* @return None.
|
|
*
|
|
****************************************************************************/
|
|
void Xil_ICacheEnable(void)
|
|
{
|
|
u32 CtrlReg;
|
|
|
|
if (EL3 == 1) {
|
|
CtrlReg = mfcp(SCTLR_EL3);
|
|
} else if (EL1_NONSECURE == 1) {
|
|
CtrlReg = mfcp(SCTLR_EL1);
|
|
} else {
|
|
CtrlReg = 0U;
|
|
}
|
|
|
|
/* enable caches only if they are disabled */
|
|
if((CtrlReg & XREG_CONTROL_ICACHE_BIT)==0x00000000U){
|
|
/* invalidate the instruction cache */
|
|
Xil_ICacheInvalidate();
|
|
|
|
CtrlReg |= XREG_CONTROL_ICACHE_BIT;
|
|
|
|
if (EL3 == 1) {
|
|
/* enable the instruction cache for el3*/
|
|
mtcp(SCTLR_EL3,CtrlReg);
|
|
} else if (EL1_NONSECURE == 1) {
|
|
/* enable the instruction cache for el1*/
|
|
mtcp(SCTLR_EL1,CtrlReg);
|
|
}
|
|
}
|
|
}
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* @brief Disable the instruction cache.
|
|
*
|
|
* @return None.
|
|
*
|
|
****************************************************************************/
|
|
void Xil_ICacheDisable(void)
|
|
{
|
|
u32 CtrlReg;
|
|
|
|
if (EL3 == 1) {
|
|
CtrlReg = mfcp(SCTLR_EL3);
|
|
} else if (EL1_NONSECURE == 1) {
|
|
CtrlReg = mfcp(SCTLR_EL1);
|
|
} else {
|
|
CtrlReg = 0U;
|
|
}
|
|
/* invalidate the instruction cache */
|
|
Xil_ICacheInvalidate();
|
|
CtrlReg &= ~(XREG_CONTROL_ICACHE_BIT);
|
|
|
|
if (EL3 == 1) {
|
|
/* disable the instruction cache */
|
|
mtcp(SCTLR_EL3,CtrlReg);
|
|
} else if (EL1_NONSECURE == 1) {
|
|
/* disable the instruction cache */
|
|
mtcp(SCTLR_EL1,CtrlReg);
|
|
}
|
|
|
|
|
|
}
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* @brief Invalidate the entire instruction cache.
|
|
*
|
|
* @return None.
|
|
*
|
|
****************************************************************************/
|
|
void Xil_ICacheInvalidate(void)
|
|
{
|
|
unsigned int currmask;
|
|
currmask = mfcpsr();
|
|
mtcpsr(currmask | IRQ_FIQ_MASK);
|
|
mtcp(CSSELR_EL1,0x1);
|
|
dsb();
|
|
/* invalidate the instruction cache */
|
|
mtcpicall(IALLU);
|
|
/* Wait for invalidate to complete */
|
|
dsb();
|
|
mtcpsr(currmask);
|
|
}
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* @brief Invalidate an instruction cache line. If the instruction specified
|
|
* by the parameter adr is cached by the instruction cache, the
|
|
* cacheline containing that instruction is invalidated.
|
|
*
|
|
* @param adr: 64bit address of the instruction to be invalidated.
|
|
*
|
|
* @return None.
|
|
*
|
|
* @note The bottom 6 bits are set to 0, forced by architecture.
|
|
*
|
|
****************************************************************************/
|
|
void Xil_ICacheInvalidateLine(INTPTR adr)
|
|
{
|
|
u32 currmask;
|
|
currmask = mfcpsr();
|
|
mtcpsr(currmask | IRQ_FIQ_MASK);
|
|
|
|
mtcp(CSSELR_EL1,0x1);
|
|
/*Invalidate I Cache line*/
|
|
mtcpic(IVAU,adr & (~0x3F));
|
|
/* Wait for invalidate to complete */
|
|
dsb();
|
|
mtcpsr(currmask);
|
|
}
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* @brief Invalidate the instruction cache for the given address range.
|
|
* If the instructions specified by the address range are cached by
|
|
* the instrunction cache, the cachelines containing those
|
|
* instructions are invalidated.
|
|
*
|
|
* @param adr: 64bit start address of the range to be invalidated.
|
|
* @param len: Length of the range to be invalidated in bytes.
|
|
*
|
|
* @return None.
|
|
*
|
|
****************************************************************************/
|
|
void Xil_ICacheInvalidateRange(INTPTR adr, INTPTR len)
|
|
{
|
|
const INTPTR cacheline = 64U;
|
|
INTPTR end;
|
|
INTPTR tempadr = adr;
|
|
INTPTR tempend;
|
|
u32 currmask;
|
|
currmask = mfcpsr();
|
|
mtcpsr(currmask | IRQ_FIQ_MASK);
|
|
|
|
if (len != 0x00000000U) {
|
|
end = tempadr + len;
|
|
tempend = end;
|
|
tempadr &= ~(cacheline - 0x00000001U);
|
|
|
|
/* Select cache Level 0 I-cache in CSSR */
|
|
mtcp(CSSELR_EL1,0x1);
|
|
while (tempadr < tempend) {
|
|
/*Invalidate I Cache line*/
|
|
mtcpic(IVAU,adr & (~0x3F));
|
|
|
|
tempadr += cacheline;
|
|
}
|
|
}
|
|
/* Wait for invalidate to complete */
|
|
dsb();
|
|
mtcpsr(currmask);
|
|
}
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* @brief Configure the maximum number of outstanding data prefetches
|
|
* allowed in L1 cache.
|
|
*
|
|
* @param num: maximum number of outstanding data prefetches allowed,
|
|
* valid values are 0-7.
|
|
*
|
|
* @return None.
|
|
*
|
|
* @note This function is implemented only for EL3 privilege level.
|
|
*
|
|
*****************************************************************************/
|
|
void Xil_ConfigureL1Prefetch (u8 num) {
|
|
#if EL3
|
|
u64 val=0;
|
|
|
|
val= mfcp(S3_1_C15_C2_0 );
|
|
val &= ~(L1_DATA_PREFETCH_CONTROL_MASK);
|
|
val |= (num << L1_DATA_PREFETCH_CONTROL_SHIFT);
|
|
mtcp(S3_1_C15_C2_0,val);
|
|
#endif
|
|
}
|