forked from Imagelibrary/rtems
584 lines
20 KiB
C
584 lines
20 KiB
C
/******************************************************************************
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* Copyright (C) 2015 - 2022 Xilinx, Inc. All rights reserved.
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* SPDX-License-Identifier: MIT
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xnandpsu.h
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* @addtogroup Overview
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* @{
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* @details
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*
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* This file implements a driver to support Arasan NAND controller
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* present in Zynq Ultrascale Mp.
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*
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* <b>Driver Initialization</b>
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*
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* The function call XNandPsu_CfgInitialize() should be called by the application
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* before any other function in the driver. The initialization function takes
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* device specific data (like device id, instance id, and base address) and
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* initializes the XNandPsu instance with the device specific data.
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*
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* <b>Device Geometry</b>
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*
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* NAND flash device is memory device and it is segmented into areas called
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* Logical Unit(s) (LUN) and further in to blocks and pages. A NAND flash device
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* can have multiple LUN. LUN is sequential raw of multiple blocks of the same
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* size. A block is the smallest erasable unit of data within the Flash array of
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* a LUN. The size of each block is based on a power of 2. There is no
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* restriction on the number of blocks within the LUN. A block contains a number
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* of pages. A page is the smallest addressable unit for read and program
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* operations. The arrangement of LUN, blocks, and pages is referred to by this
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* module as the part's geometry.
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*
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* The cells within the part can be programmed from a logic 1 to a logic 0
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* and not the other way around. To change a cell back to a logic 1, the
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* entire block containing that cell must be erased. When a block is erased
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* all bytes contain the value 0xFF. The number of times a block can be
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* erased is finite. Eventually the block will wear out and will no longer
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* be capable of erasure. As of this writing, the typical flash block can
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* be erased 100,000 or more times.
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*
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* The jobs done by this driver typically are:
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* - 8-bit operational mode
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* - Read, Write, and Erase operation
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*
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* <b>Write Operation</b>
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*
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* The write call can be used to write a minimum of one byte and a maximum
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* entire flash. If the address offset specified to write is out of flash or if
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* the number of bytes specified from the offset exceed flash boundaries
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* an error is reported back to the user. The write is blocking in nature in that
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* the control is returned back to user only after the write operation is
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* completed successfully or an error is reported.
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*
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* <b>Read Operation</b>
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*
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* The read call can be used to read a minimum of one byte and maximum of
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* entire flash. If the address offset specified to read is out of flash or if
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* the number of bytes specified from the offset exceed flash boundaries
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* an error is reported back to the user. The read is blocking in nature in that
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* the control is returned back to user only after the read operation is
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* completed successfully or an error is reported.
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*
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* <b>Erase Operation</b>
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*
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* The erase operations are provided to erase a Block in the Flash memory. The
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* erase call is blocking in nature in that the control is returned back to user
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* only after the erase operation is completed successfully or an error is
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* reported.
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*
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* @note Driver has been renamed to nandpsu after change in
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* naming convention.
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*
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* This driver is intended to be RTOS and processor independent. It works with
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* physical addresses only. Any needs for dynamic memory management, threads,
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* mutual exclusion, virtual memory, cache control, or HW write protection
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* management must be satisfied by the layer above this driver.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- ---------- -----------------------------------------------
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* 1.0 nm 05/06/2014 First release
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* 2.0 sb 01/12/2015 Removed Null checks for Buffer passed
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* as parameter to Read API's
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* - XNandPsu_Read()
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* - XNandPsu_ReadPage
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* Modified
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* - XNandPsu_SetFeature()
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* - XNandPsu_GetFeature()
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* and made them public.
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* Removed Failure Return for BCF Error check in
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* XNandPsu_ReadPage() and added BCH_Error counter
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* in the instance pointer structure.
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* Added XNandPsu_Prepare_Cmd API
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* Replaced
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* - XNandPsu_IntrStsEnable
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* - XNandPsu_IntrStsClear
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* - XNandPsu_IntrClear
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* - XNandPsu_SetProgramReg
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* with XNandPsu_WriteReg call
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* Modified xnandpsu.c file API's with above changes.
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* Corrected the program command for Set Feature API.
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* Modified
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* - XNandPsu_OnfiReadStatus
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* - XNandPsu_GetFeature
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* - XNandPsu_SetFeature
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* to add support for DDR mode.
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* Changed Convention for SLC/MLC
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* SLC --> HAMMING
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* MLC --> BCH
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* SlcMlc --> IsBCH
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* Added support for writing BBT signature and version
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* in page section by enabling XNANDPSU_BBT_NO_OOB.
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* Removed extra DMA mode initialization from
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* the XNandPsu_CfgInitialize API.
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* Modified
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* - XNandPsu_SetEccAddrSize
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* ECC address now is calculated based upon the
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* size of spare area
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* Modified Block Erase API, removed clearing of
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* packet register before erase.
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* Clearing Data Interface Register before
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* XNandPsu_OnfiReset call.
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* Modified XNandPsu_ChangeTimingMode API supporting
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* SDR and NVDDR interface for timing modes 0 to 5.
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* Modified Bbt Signature and Version Offset value for
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* Oob and No-Oob region.
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* 1.0 kpc 17/06/2015 Increased the timeout for complete event to avoid
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* timeout errors for erase operation on slower devices.
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* 1.1 mi 09/16/16 Removed compilation warnings with extra compiler flags.
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* 1.1 nsk 11/07/16 Change memcpy to Xil_MemCpy, CR#960462
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* 1.2 nsk 01/19/17 Fix for the failure of reading nand first redundant
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* parameter page. CR#966603
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* ms 02/12/17 Fix for the compilation warning in _g.c file.
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* ms 03/17/17 Added readme.txt file in examples folder for doxygen
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* generation.
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* ms 04/10/17 Modified Comment lines in nandpsu_example.c to
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* follow doxygen rules.
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* 1.2 nsk 08/08/17 Added support to import example in SDK
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* 1.4 nsk 04/10/18 Added ICCARM compiler support. CR#997552.
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* 1.5 mus 11/08/18 Updated BBT signature array size in
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* XNandPsu_BbtDesc structure to fix the compilation
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* warnings.
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# 1.6 sd 06/02/20 Added Clock support
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* 1.6 sd 20/03/20 Added compilation flag
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* 1.8 sg 03/18/21 Added validation check for parameter page.
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* 1.9 akm 07/15/21 Initialize NandInstPtr with Data Interface & Timing mode info.
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* 1.10 akm 10/20/21 Fix gcc warnings.
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* 1.10 akm 12/21/21 Validate input parameters before use.
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* 1.10 akm 01/05/22 Remove assert checks form static and internal APIs.
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* 1.11 akm 03/31/22 Fix unused parameter warning.
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* 1.11 akm 03/31/22 Fix misleading-indentation warning.
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*
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* </pre>
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*
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******************************************************************************/
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#ifndef XNANDPSU_H /* prevent circular inclusions */
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#define XNANDPSU_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_types.h"
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#include <string.h>
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#include "xstatus.h"
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#include "xil_assert.h"
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#include "xnandpsu_hw.h"
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#include "xnandpsu_onfi.h"
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#include "xil_cache.h"
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#if defined (XCLOCKING)
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#include "xil_clocking.h"
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#endif
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/************************** Constant Definitions *****************************/
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#define XNANDPSU_DEBUG
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#define XNANDPSU_MAX_TARGETS 1U /**< ce_n0, ce_n1 */
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#define XNANDPSU_MAX_PKT_SIZE 0x7FFU /**< Max packet size */
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#define XNANDPSU_MAX_PKT_COUNT 0xFFFU /**< Max packet count */
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#define XNANDPSU_PAGE_SIZE_512 512U /**< 512 bytes page */
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#define XNANDPSU_PAGE_SIZE_2K 2048U /**< 2K bytes page */
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#define XNANDPSU_PAGE_SIZE_4K 4096U /**< 4K bytes page */
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#define XNANDPSU_PAGE_SIZE_8K 8192U /**< 8K bytes page */
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#define XNANDPSU_PAGE_SIZE_16K 16384U /**< 16K bytes page */
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#define XNANDPSU_PAGE_SIZE_1K_16BIT 1024U /**< 16-bit 2K bytes page */
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#define XNANDPSU_MAX_PAGE_SIZE 16384U /**< Max page size supported */
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#define XNANDPSU_HAMMING 0x1U /**< Hamming Flash */
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#define XNANDPSU_BCH 0x2U /**< BCH Flash */
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#define XNANDPSU_MAX_BLOCKS 16384U /**< Max number of Blocks */
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#define XNANDPSU_MAX_SPARE_SIZE 0x800U /**< Max spare bytes of a NAND
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flash page of 16K */
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#define XNANDPSU_MAX_LUNS 8U /**< Max number of LUNs */
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#define XNANDPSU_MAX_PAGES_PER_BLOCK 512U /**< Max number pages per block */
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#define XNANDPSU_INTR_POLL_TIMEOUT 0xF000000U
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#define XNANDPSU_SDR_CLK ((u16)100U * (u16)1000U * (u16)1000U)
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#define XNANDPSU_NVDDR_CLK_0 ((u16)20U * (u16)1000U * (u16)1000U)
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#define XNANDPSU_NVDDR_CLK_1 ((u16)33U * (u16)1000U * (u16)1000U)
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#define XNANDPSU_NVDDR_CLK_2 ((u16)50U * (u16)1000U * (u16)1000U)
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#define XNANDPSU_NVDDR_CLK_3 ((u16)66U * (u16)1000U * (u16)1000U)
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#define XNANDPSU_NVDDR_CLK_4 ((u16)83U * (u16)1000U * (u16)1000U)
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#define XNANDPSU_NVDDR_CLK_5 ((u16)100U * (u16)1000U * (u16)1000U)
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#define XNANDPSU_MAX_TIMING_MODE 5
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/**
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* The XNandPsu_Config structure contains configuration information for NAND
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* controller.
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*/
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typedef struct {
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u16 DeviceId; /**< Instance ID of NAND flash controller */
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u32 BaseAddress; /**< Base address of NAND flash controller */
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u8 IsCacheCoherent; /**< Describes whether Cache Coherent or not */
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#if defined (XCLOCKING)
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u32 RefClk; /**< Input clocks */
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#endif
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} XNandPsu_Config;
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/**
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* The XNandPsu_DataInterface enum contains flash operating mode.
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*/
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typedef enum {
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XNANDPSU_SDR = 0U, /**< Single Data Rate */
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XNANDPSU_NVDDR /**< Double Data Rate */
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} XNandPsu_DataInterface;
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/**
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* XNandPsu_TimingMode enum contains timing modes.
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*/
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typedef enum {
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XNANDPSU_SDR0 = 0U,
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XNANDPSU_SDR1,
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XNANDPSU_SDR2,
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XNANDPSU_SDR3,
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XNANDPSU_SDR4,
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XNANDPSU_SDR5,
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XNANDPSU_NVDDR0,
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XNANDPSU_NVDDR1,
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XNANDPSU_NVDDR2,
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XNANDPSU_NVDDR3,
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XNANDPSU_NVDDR4,
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XNANDPSU_NVDDR5
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} XNandPsu_TimingMode;
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/**
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* The XNandPsu_SWMode enum contains the driver operating mode.
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*/
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typedef enum {
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XNANDPSU_POLLING = 0, /**< Polling */
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XNANDPSU_INTERRUPT /**< Interrupt */
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} XNandPsu_SWMode;
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/**
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* The XNandPsu_DmaMode enum contains the controller MDMA mode.
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*/
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typedef enum {
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XNANDPSU_PIO = 0, /**< PIO Mode */
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XNANDPSU_SDMA, /**< SDMA Mode */
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XNANDPSU_MDMA /**< MDMA Mode */
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} XNandPsu_DmaMode;
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/**
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* The XNandPsu_EccMode enum contains ECC functionality.
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*/
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typedef enum {
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XNANDPSU_NONE = 0,
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XNANDPSU_HWECC,
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XNANDPSU_EZNAND,
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XNANDPSU_ONDIE
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} XNandPsu_EccMode;
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/**
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* Bad block table descriptor
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*/
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typedef struct {
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u32 PageOffset[XNANDPSU_MAX_TARGETS];
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/**< Page offset where BBT resides */
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u32 SigOffset; /**< Signature offset in Spare area */
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u32 VerOffset; /**< Offset of BBT version */
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u32 SigLength; /**< Length of the signature */
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u32 MaxBlocks; /**< Max blocks to search for BBT */
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char Signature[5]; /**< BBT signature */
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u8 Version[XNANDPSU_MAX_TARGETS];
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/**< BBT version */
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u32 Valid; /**< BBT descriptor is valid or not */
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} XNandPsu_BbtDesc;
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/**
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* Bad block pattern
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*/
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typedef struct {
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u32 Options; /**< Options to search the bad block pattern */
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u32 Offset; /**< Offset to search for specified pattern */
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u32 Length; /**< Number of bytes to check the pattern */
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u8 Pattern[2]; /**< Pattern format to search for */
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} XNandPsu_BadBlockPattern;
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/**
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* The XNandPsu_Geometry structure contains the ONFI geometry information.
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*/
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typedef struct {
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/* Parameter page information */
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u32 BytesPerPage; /**< Number of bytes per page */
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u16 SpareBytesPerPage; /**< Number of spare bytes per page */
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u32 PagesPerBlock; /**< Number of pages per block */
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u32 BlocksPerLun; /**< Number of blocks per LUN */
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u8 NumLuns; /**< Number of LUN's */
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u8 RowAddrCycles; /**< Row address cycles */
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u8 ColAddrCycles; /**< Column address cycles */
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u8 NumBitsPerCell; /**< Number of bits per cell (Hamming/BCH) */
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u8 NumBitsECC; /**< Number of bits ECC correctability */
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u32 EccCodeWordSize; /**< ECC codeword size */
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/* Driver specific information */
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u32 BlockSize; /**< Block size */
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u32 NumTargetPages; /**< Total number of pages in a Target */
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u32 NumTargetBlocks; /**< Total number of blocks in a Target */
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u64 TargetSize; /**< Target size in bytes */
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u8 NumTargets; /**< Number of targets present */
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u32 NumPages; /**< Total number of pages */
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u32 NumBlocks; /**< Total number of blocks */
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u64 DeviceSize; /**< Total flash size in bytes */
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} XNandPsu_Geometry;
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/**
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* The XNandPsu_Features structure contains the ONFI features information.
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*/
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typedef struct {
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u32 NvDdr;
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u32 EzNand;
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u32 OnDie;
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u32 ExtPrmPage;
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} XNandPsu_Features;
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/**
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* The XNandPsu_EccMatrix structure contains ECC features information.
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*/
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typedef struct {
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u16 PageSize;
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u16 CodeWordSize;
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u8 NumEccBits;
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u8 IsBCH;
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u16 EccAddr;
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u16 EccSize;
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} XNandPsu_EccMatrix;
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/**
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* The XNandPsu_EccCfg structure contains ECC configuration.
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*/
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typedef struct {
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u16 EccAddr;
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u16 EccSize;
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u16 CodeWordSize;
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u8 NumEccBits;
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u8 IsBCH;
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} XNandPsu_EccCfg;
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/**
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* The XNandPsu structure contains the driver instance data. The user is
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* required to allocate a variable of this type for the NAND controller.
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* A pointer to a variable of this type is then passed to the driver API
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* functions.
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*/
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#ifdef __ICCARM__
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#pragma pack(push, 1)
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#endif
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typedef struct {
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u32 IsReady; /**< Device is initialized and ready */
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XNandPsu_Config Config;
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u32 Ecc_Stat_PerPage_flips; /**< Ecc Correctable Error Counter for Current Page */
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u32 Ecc_Stats_total_flips; /**< Total Ecc Errors Corrected */
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XNandPsu_DataInterface DataInterface;
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XNandPsu_TimingMode TimingMode;
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XNandPsu_SWMode Mode; /**< Driver operating mode */
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XNandPsu_DmaMode DmaMode; /**< MDMA mode enabled/disabled */
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XNandPsu_EccMode EccMode; /**< ECC Mode */
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XNandPsu_EccCfg EccCfg; /**< ECC configuration */
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XNandPsu_Geometry Geometry; /**< Flash geometry */
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XNandPsu_Features Features; /**< ONFI features */
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#ifdef __ICCARM__
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u8 PartialDataBuf[XNANDPSU_MAX_PAGE_SIZE]; /**< Partial read/write buffer */
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#pragma pack(pop)
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#else
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u8 PartialDataBuf[XNANDPSU_MAX_PAGE_SIZE] __attribute__ ((aligned(64)));
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#endif
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/* Bad block table definitions */
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XNandPsu_BbtDesc BbtDesc; /**< Bad block table descriptor */
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XNandPsu_BbtDesc BbtMirrorDesc; /**< Mirror BBT descriptor */
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XNandPsu_BadBlockPattern BbPattern; /**< Bad block pattern to
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search */
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u8 Bbt[XNANDPSU_MAX_BLOCKS >> 2]; /**< Bad block table array */
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} XNandPsu;
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/******************* Macro Definitions (Inline Functions) *******************/
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/*****************************************************************************/
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/**
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* This macro sets the bitmask in the register.
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*
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* @param InstancePtr is a pointer to the XNandPsu instance of the
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* controller.
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* @param RegOffset is the register offset.
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* @param BitMask is the bitmask.
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*
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* @note C-style signature:
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* void XNandPsu_SetBits(XNandPsu *InstancePtr, u32 RegOffset,
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* u32 BitMask)
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*
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*****************************************************************************/
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#define XNandPsu_SetBits(InstancePtr, RegOffset, BitMask) \
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XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
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(RegOffset), \
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((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress, \
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(RegOffset)) | (BitMask))))
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/*****************************************************************************/
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/**
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* This macro clears the bitmask in the register.
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*
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* @param InstancePtr is a pointer to the XNandPsu instance of the
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* controller.
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* @param RegOffset is the register offset.
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* @param BitMask is the bitmask.
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*
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* @note C-style signature:
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* void XNandPsu_ClrBits(XNandPsu *InstancePtr, u32 RegOffset,
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* u32 BitMask)
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*
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*****************************************************************************/
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#define XNandPsu_ClrBits(InstancePtr, RegOffset, BitMask) \
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XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
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(RegOffset), \
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((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress, \
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(RegOffset)) & ~(BitMask))))
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/*****************************************************************************/
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/**
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* This macro clears and updates the bitmask in the register.
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*
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* @param InstancePtr is a pointer to the XNandPsu instance of the
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* controller.
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* @param RegOffset is the register offset.
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* @param Mask is the bitmask.
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* @param Value is the register value to write.
|
|
*
|
|
* @note C-style signature:
|
|
* void XNandPsu_ReadModifyWrite(XNandPsu *InstancePtr,
|
|
* u32 RegOffset, u32 Mask, u32 Val)
|
|
*
|
|
*****************************************************************************/
|
|
#define XNandPsu_ReadModifyWrite(InstancePtr, RegOffset, Mask, Value) \
|
|
XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
|
|
(RegOffset), \
|
|
((u32)((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,\
|
|
(u32)(RegOffset)) & (u32)(~(Mask))) | (u32)(Value))))
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
* This macro enables bitmask in Interrupt Signal Enable register.
|
|
*
|
|
* @param InstancePtr is a pointer to the XNandPsu instance of the
|
|
* controller.
|
|
* @param Mask is the bitmask.
|
|
*
|
|
* @note C-style signature:
|
|
* void XNandPsu_IntrSigEnable(XNandPsu *InstancePtr, u32 Mask)
|
|
*
|
|
*****************************************************************************/
|
|
#define XNandPsu_IntrSigEnable(InstancePtr, Mask) \
|
|
XNandPsu_SetBits((InstancePtr), \
|
|
XNANDPSU_INTR_SIG_EN_OFFSET, \
|
|
(Mask))
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
* This macro clears bitmask in Interrupt Signal Enable register.
|
|
*
|
|
* @param InstancePtr is a pointer to the XNandPsu instance of the
|
|
* controller.
|
|
* @param Mask is the bitmask.
|
|
*
|
|
* @note C-style signature:
|
|
* void XNandPsu_IntrSigClear(XNandPsu *InstancePtr, u32 Mask)
|
|
*
|
|
*****************************************************************************/
|
|
#define XNandPsu_IntrSigClear(InstancePtr, Mask) \
|
|
XNandPsu_ClrBits((InstancePtr), \
|
|
XNANDPSU_INTR_SIG_EN_OFFSET, \
|
|
(Mask))
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
* This macro enables bitmask in Interrupt Status Enable register.
|
|
*
|
|
* @param InstancePtr is a pointer to the XNandPsu instance of the
|
|
* controller.
|
|
* @param Mask is the bitmask.
|
|
*
|
|
* @note C-style signature:
|
|
* void XNandPsu_IntrStsEnable(XNandPsu *InstancePtr, u32 Mask)
|
|
*
|
|
*****************************************************************************/
|
|
#define XNandPsu_IntrStsEnable(InstancePtr, Mask) \
|
|
XNandPsu_SetBits((InstancePtr), \
|
|
XNANDPSU_INTR_STS_EN_OFFSET, \
|
|
(Mask))
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
* This macro checks for the ONFI ID.
|
|
*
|
|
* @param Buff is the buffer holding ONFI ID
|
|
*
|
|
* @note none.
|
|
*
|
|
*****************************************************************************/
|
|
#define IS_ONFI(Buff) \
|
|
((Buff)[0] == (u8)'O') && ((Buff)[1] == (u8)'N') && \
|
|
((Buff)[2] == (u8)'F') && ((Buff)[3] == (u8)'I')
|
|
|
|
/************************** Function Prototypes *****************************/
|
|
|
|
s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr,
|
|
u32 EffectiveAddr);
|
|
|
|
s32 XNandPsu_Erase(XNandPsu *InstancePtr, u64 Offset, u64 Length);
|
|
|
|
s32 XNandPsu_Write(XNandPsu *InstancePtr, u64 Offset, u64 Length,
|
|
u8 *SrcBuf);
|
|
|
|
s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length,
|
|
u8 *DestBuf);
|
|
|
|
s32 XNandPsu_EraseBlock(XNandPsu *InstancePtr, u32 Target, u32 Block);
|
|
|
|
s32 XNandPsu_WriteSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf);
|
|
|
|
s32 XNandPsu_ReadSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf);
|
|
|
|
s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr,
|
|
XNandPsu_DataInterface NewIntf,
|
|
XNandPsu_TimingMode NewMode);
|
|
|
|
s32 XNandPsu_GetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
|
|
u8 *Buf);
|
|
|
|
s32 XNandPsu_SetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
|
|
u8 *Buf);
|
|
|
|
s32 XNandPsu_ScanBbt(XNandPsu *InstancePtr);
|
|
|
|
s32 XNandPsu_MarkBlockBad(XNandPsu *InstancePtr, u32 Block);
|
|
|
|
void XNandPsu_EnableDmaMode(XNandPsu *InstancePtr);
|
|
|
|
void XNandPsu_DisableDmaMode(XNandPsu *InstancePtr);
|
|
|
|
void XNandPsu_EnableEccMode(XNandPsu *InstancePtr);
|
|
|
|
void XNandPsu_DisableEccMode(XNandPsu *InstancePtr);
|
|
|
|
void XNandPsu_Prepare_Cmd(XNandPsu *InstancePtr, u8 Cmd1, u8 Cmd2, u8 EccState,
|
|
u8 DmaMode, u8 AddrCycles);
|
|
|
|
/* XNandPsu_LookupConfig in xnandpsu_sinit.c */
|
|
XNandPsu_Config *XNandPsu_LookupConfig(u16 DevID);
|
|
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* XNANDPSU_H end of protection macro */
|
|
/** @} */
|