forked from Imagelibrary/rtems
ab8817ca03
Add directives to get and set the priority of an interrupt vector. Implement the directives for the following BSP families: * arm/lpc24xx * arm/lpc32xx * powerpc/mpc55xxevb * powerpc/qoriq Implement the directives for the following interrupt controllers: * GICv2 and GICv3 (arm and aarch64) * NVIC (arm) * PLIC (riscv) Update #5002.
311 lines
8.1 KiB
C
311 lines
8.1 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* RTEMS TQM8xx BSP
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*
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* This file contains the console driver.
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*
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* Derived from: generic MPC83xx BSP
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*/
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/*
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* Copyright (c) 2008 Thomas Doerfler, embedded brains GmbH & Co. KG
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <rtems.h>
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#include <mpc8xx.h>
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#include <libcpu/powerpc-utility.h>
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#include <bsp/vectors.h>
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#include <bsp.h>
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#include <bsp/irq.h>
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#include <bsp/irq-generic.h>
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/*
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* functions to enable/disable a source at the SIU/CPM irq controller
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*/
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static rtems_status_code bsp_irq_disable_at_SIU(rtems_vector_number irqnum)
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{
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rtems_vector_number vecnum = irqnum - BSP_SIU_IRQ_LOWEST_OFFSET;
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m8xx.simask &= ~(1 << (31 - vecnum));
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return RTEMS_SUCCESSFUL;
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}
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static rtems_status_code bsp_irq_enable_at_SIU(rtems_vector_number irqnum)
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{
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rtems_vector_number vecnum = irqnum - BSP_SIU_IRQ_LOWEST_OFFSET;
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m8xx.simask |= (1 << (31 - vecnum));
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return RTEMS_SUCCESSFUL;
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}
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static rtems_status_code bsp_irq_disable_at_CPM(rtems_vector_number irqnum)
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{
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rtems_vector_number vecnum = irqnum - BSP_CPM_IRQ_LOWEST_OFFSET;
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m8xx.cimr &= ~(1 << (vecnum));
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return RTEMS_SUCCESSFUL;
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}
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static rtems_status_code bsp_irq_enable_at_CPM(rtems_vector_number irqnum)
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{
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rtems_vector_number vecnum = irqnum - BSP_CPM_IRQ_LOWEST_OFFSET;
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m8xx.cimr |= (1 << (vecnum));
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code bsp_interrupt_get_attributes(
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rtems_vector_number vector,
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rtems_interrupt_attributes *attributes
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)
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{
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code bsp_interrupt_is_pending(
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rtems_vector_number vector,
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bool *pending
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)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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bsp_interrupt_assert(pending != NULL);
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*pending = false;
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return RTEMS_UNSATISFIED;
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}
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rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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return RTEMS_UNSATISFIED;
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}
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rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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return RTEMS_UNSATISFIED;
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}
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rtems_status_code bsp_interrupt_vector_is_enabled(
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rtems_vector_number vector,
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bool *enabled
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)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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bsp_interrupt_assert(enabled != NULL);
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*enabled = false;
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return RTEMS_UNSATISFIED;
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}
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rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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if (BSP_IS_CPM_IRQ(vector)) {
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bsp_irq_enable_at_CPM(vector);
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} else if (BSP_IS_SIU_IRQ(vector)) {
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bsp_irq_enable_at_SIU(vector);
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}
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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if (BSP_IS_CPM_IRQ(vector)) {
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bsp_irq_disable_at_CPM(vector);
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} else if (BSP_IS_SIU_IRQ(vector)) {
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bsp_irq_disable_at_SIU(vector);
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}
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code bsp_interrupt_set_priority(
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rtems_vector_number vector,
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uint32_t priority
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)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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return RTEMS_UNSATISFIED;
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}
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rtems_status_code bsp_interrupt_get_priority(
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rtems_vector_number vector,
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uint32_t *priority
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)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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bsp_interrupt_assert(priority != NULL);
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return RTEMS_UNSATISFIED;
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}
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/*
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* IRQ Handler: this is called from the primary exception dispatcher
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*/
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static int BSP_irq_handle_at_cpm(void)
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{
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int32_t cpvecnum;
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uint32_t msr;
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/* Get vector number: write IACK=1, then read vectir */
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m8xx.civr = 1;
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cpvecnum = (m8xx.civr >> 11) + BSP_CPM_IRQ_LOWEST_OFFSET;
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/*
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* Check the vector number,
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* enable exceptions and dispatch the handler.
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* NOTE: lower-prio interrupts are automatically masked in CPIC
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*/
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if (BSP_IS_CPM_IRQ(cpvecnum)) {
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/* Enable all interrupts */
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msr = ppc_external_exceptions_enable();
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/* Dispatch interrupt handlers */
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bsp_interrupt_handler_dispatch(cpvecnum);
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/* Restore machine state */
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ppc_external_exceptions_disable(msr);
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}
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else {
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/* not valid vector */
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bsp_interrupt_handler_default(cpvecnum);
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}
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/*
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* clear "in-service" bit
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*/
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m8xx.cisr = 1 << (cpvecnum - BSP_CPM_IRQ_LOWEST_OFFSET);
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return 0;
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}
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static int BSP_irq_handle_at_siu( unsigned excNum)
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{
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int32_t sivecnum;
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uint32_t msr;
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bool is_cpm_irq;
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uint32_t simask_save;
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/*
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* check, if interrupt is pending
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* and repeat as long as valid interrupts are pending
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*/
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while (0 != (m8xx.simask & m8xx.sipend)) {
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/* Get vector number */
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sivecnum = (m8xx.sivec >> 26);
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is_cpm_irq = (sivecnum == BSP_CPM_INTERRUPT);
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/*
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* Check the vector number, mask lower priority interrupts, enable
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* exceptions and dispatch the handler.
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*/
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if (BSP_IS_SIU_IRQ(sivecnum)) {
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simask_save = m8xx.simask;
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/*
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* if this is the CPM interrupt, mask lower prio interrupts at SIU
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* else mask lower and same priority interrupts
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*/
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m8xx.simask &= ~0 << (32
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- sivecnum
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- ((is_cpm_irq) ? 1 : 0));
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if (is_cpm_irq) {
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BSP_irq_handle_at_cpm();
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}
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else {
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/* Enable all interrupts */
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msr = ppc_external_exceptions_enable();
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/* Dispatch interrupt handlers */
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bsp_interrupt_handler_dispatch(sivecnum + BSP_SIU_IRQ_LOWEST_OFFSET);
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/* Restore machine state */
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ppc_external_exceptions_disable(msr);
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/*
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* clear pending bit, if edge triggered interrupt input
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*/
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m8xx.sipend = 1 << (31 - sivecnum);
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}
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/* Restore initial masks */
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m8xx.simask = simask_save;
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} else {
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/* not valid vector */
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bsp_interrupt_handler_default(sivecnum);
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}
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}
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return 0;
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}
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/*
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* Activate the CPIC
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*/
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static void mpc8xx_cpic_initialize( void)
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{
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rtems_status_code sc;
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/*
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* mask off all interrupts
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*/
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m8xx.cimr = 0;
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/*
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* make sure CPIC request proper level at SIU interrupt controller
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*/
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m8xx.cicr = (0x00e41f80 |
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((BSP_CPM_INTERRUPT/2) << 13));
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/*
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* enable CPIC interrupt in SIU interrupt controller
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*/
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sc = bsp_irq_enable_at_SIU(BSP_CPM_INTERRUPT);
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_Assert_Unused_variable_equals(sc, RTEMS_SUCCESSFUL);
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}
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/*
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* Activate the SIU interrupt controller
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*/
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static void mpc8xx_siu_int_initialize( void)
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{
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/*
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* mask off all interrupts
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*/
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m8xx.simask = 0;
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}
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static int mpc8xx_exception_handler(BSP_Exception_frame *frame,
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unsigned exception_number)
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{
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return BSP_irq_handle_at_siu(exception_number);
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}
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void bsp_interrupt_facility_initialize()
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{
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rtems_status_code sc;
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/* Install exception handler */
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sc = ppc_exc_set_handler(ASM_EXT_VECTOR, mpc8xx_exception_handler);
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_Assert_Unused_variable_equals(sc, RTEMS_SUCCESSFUL);
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/* Initialize the SIU interrupt controller */
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mpc8xx_siu_int_initialize();
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/* Initialize the CPIC interrupt controller */
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mpc8xx_cpic_initialize();
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}
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