forked from Imagelibrary/rtems
148 lines
3.5 KiB
ArmAsm
148 lines
3.5 KiB
ArmAsm
/*
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* Copyright (c) 2018 embedded brains GmbH
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* Copyright (c) 2015 University of York.
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* Hesham Almatary <hesham@alumni.york.ac.uk>
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*
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* Copyright (c) 2013, The Regents of the University of California (Regents).
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* All Rights Reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <rtems/asm.h>
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#include <rtems/score/percpu.h>
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#include <rtems/score/riscv-utility.h>
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#include <bsp/linker-symbols.h>
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#include <bspopts.h>
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PUBLIC(_start)
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.section .bsp_start_text, "wax", @progbits
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.align 2
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TYPE_FUNC(_start)
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SYM(_start):
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/* Load global pointer */
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.option push
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.option norelax
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LADDR gp, __global_pointer$
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.option pop
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/* Init FPU */
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#ifdef __riscv_flen
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li t0, MSTATUS_FS
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csrs mstatus, t0
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csrw fcsr, zero
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#endif
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/* Set exception handler */
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LADDR t0, _RISCV_Exception_handler
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csrw mtvec, t0
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/* Load stack pointer and branch to secondary processor start if necessary */
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#ifdef RTEMS_SMP
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LADDR sp, _ISR_Stack_area_begin
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LADDR t2, _ISR_Stack_size
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csrr s0, mhartid
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LADDR t0, _Per_CPU_Information
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slli t1, s0, PER_CPU_CONTROL_SIZE_LOG2
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add s1, t0, t1
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csrw mscratch, s1
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bnez s0, .Lstart_on_secondary_processor
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add sp, sp, t2
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#else
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LADDR sp, _ISR_Stack_area_end
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#endif
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#ifdef BSP_START_COPY_FDT_FROM_U_BOOT
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mv a0, a1
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call bsp_fdt_copy
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#endif
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/* Clear .bss */
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LADDR a0, bsp_section_bss_begin
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li a1, 0
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LADDR a2, bsp_section_bss_size
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call memset
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#ifdef RTEMS_SMP
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/* Give go to secondary processors */
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LADDR t0, .Lsecondary_processor_go
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fence iorw,ow
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amoswap.w zero, zero, 0(t0)
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#endif
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li a0, 0
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j boot_card
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#ifdef RTEMS_SMP
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.Lstart_on_secondary_processor:
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/* Adjust stack pointer */
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#ifdef __riscv_mul
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addi t0, s0, 1
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mul t2, t2, t0
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#else
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mv t0, s0
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mv t3, t2
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.Ladd_more:
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add t2, t2, t3
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addi t0, t0, -1
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bnez t0, .Ladd_more
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#endif
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add sp, sp, t2
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/* Wait for go issued by the boot processor (mhartid == 0) */
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LADDR t0, .Lsecondary_processor_go
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.Lwait_for_go_again:
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lw t1, 0(t0)
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fence iorw, iorw
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bnez t1, .Lwait_for_go_again
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mv a0, s1
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call bsp_start_on_secondary_processor
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#if __riscv_xlen == 32
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.align 2
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#elif __riscv_xlen == 64
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.align 3
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#endif
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.Lsecondary_processor_go:
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/*
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* These are ebreak instructions, just in case we end up here executing
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* code.
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*/
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.word 0x00100073
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#if __riscv_xlen == 64
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.word 0x00100073
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#endif
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#endif /* RTEMS_SMP */
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