forked from Imagelibrary/rtems
4cf93658ef
The previous cache manager support used a single souce file (cache_manager.c) which included an implementation header (cache_.h). This required the use of specialized include paths to find the right header file. Change this to include a generic implementation header (cacheimpl.h) in specialized source files. Use the following directories and files: * bsps/shared/cache * bsps/@RTEMS_CPU@/shared/cache * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c Update #3285.
102 lines
2.4 KiB
C
102 lines
2.4 KiB
C
/*
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* COPYRIGHT (c) 1989-2008.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems.h>
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#include <mcf5235/mcf5235.h>
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#include "cache.h"
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/*
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* Default value for the cacr is set by the BSP
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*/
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extern uint32_t cacr_mode;
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/*
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* Cannot be frozen
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*/
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static void _CPU_cache_freeze_data(void) {}
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static void _CPU_cache_unfreeze_data(void) {}
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static void _CPU_cache_freeze_instruction(void) {}
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static void _CPU_cache_unfreeze_instruction(void) {}
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/*
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* Write-through data cache -- flushes are unnecessary
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*/
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static void _CPU_cache_flush_1_data_line(const void *d_addr) {}
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static void _CPU_cache_flush_entire_data(void) {}
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static void _CPU_cache_enable_instruction(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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cacr_mode &= ~MCF5XXX_CACR_DIDI;
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m68k_set_cacr(cacr_mode);
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rtems_interrupt_enable(level);
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}
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static void _CPU_cache_disable_instruction(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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cacr_mode |= MCF5XXX_CACR_DIDI;
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m68k_set_cacr(cacr_mode);
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rtems_interrupt_enable(level);
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}
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static void _CPU_cache_invalidate_entire_instruction(void)
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{
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m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
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}
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static void _CPU_cache_invalidate_1_instruction_line(const void *addr)
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{
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/*
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* Top half of cache is I-space
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*/
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addr = (void *)((int)addr | 0x400);
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__asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
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}
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static void _CPU_cache_enable_data(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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cacr_mode &= ~MCF5XXX_CACR_DISD;
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m68k_set_cacr(cacr_mode);
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rtems_interrupt_enable(level);
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}
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static void _CPU_cache_disable_data(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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cacr_mode |= MCF5XXX_CACR_DISD;
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m68k_set_cacr(cacr_mode);
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rtems_interrupt_enable(level);
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}
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static void _CPU_cache_invalidate_entire_data(void)
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{
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m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
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}
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static void _CPU_cache_invalidate_1_data_line(const void *addr)
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{
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/*
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* Bottom half of cache is D-space
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*/
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addr = (void *)((int)addr & ~0x400);
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__asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
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}
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#include "../../../shared/cache/cacheimpl.h"
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