forked from Imagelibrary/rtems
275 lines
8.6 KiB
C
275 lines
8.6 KiB
C
/**
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* @file
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*
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* @ingroup m68k_mvme
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*
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* @brief MVME16x IO definitions
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*/
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/* mvme16x_hw.h
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*
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* This include file contains all MVME16x board IO definitions
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* and was derived by combining the common items in the
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* mvme162 and mvme167 BSPs.
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*
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* COPYRIGHT (c) 1989-2000.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef __MVME16xHW_h
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#define __MVME16xHW_h
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#include <bsp.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @defgroup m68k_mvme MVME16X IO Support
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*
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* @ingroup RTEMSBSPsM68kShared
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*
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* @brief IO Support Package
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*/
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struct rtems_bsdnet_ifconfig;
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int uti596_attach(struct rtems_bsdnet_ifconfig * pConfig, int attaching );
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#define RTEMS_BSP_NETWORK_DRIVER_NAME "uti1"
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#define RTEMS_BSP_NETWORK_DRIVER_ATTACH uti596_attach
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/*
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* This is NOT the base address of local RAM!
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* This is the base local address of the VMEbus short I/O space. A local
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* access to this space results in a A16 VMEbus I/O cycle. This base address
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* is NOT configurable on the MVME167, although the types of VMEbus short I/O
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* cycles generated when a cycle in the local 0xFFFF0000-0xFFFFFFFF address
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* range is generated is under control of bits 8-15 of LCSR 0xFFF4002C. The
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* GCSRs of other boards are accessible only through the VMEbus short I/O
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* space. See pages 2-45 and 2-7.
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*/
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#define BOARD_BASE_ADDRESS 0xFFFF0000
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/*
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* This address must be added to the BOARD_BASE_ADDRESS to access the GCSR of
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* other MVMEs in the group, i.e. it represents the offset of the GCSRs in the
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* VMEbus short I/O space. It also should represent the group address of this
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* MVME167! The group address is configurable, and must match the address
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* programmed into the MVME167 through the 167Bug monitor. 0xCC is the address
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* recommended by Motorola. It is arbitrary.
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* See pages 2-42 and 2-97 to 2-104.
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*/
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#define GROUP_BASE_ADDRESS 0x0000CC00
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/*
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* Representation of the VMEchip2 LCSR.
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* Could be made more detailed.
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*/
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typedef volatile struct {
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unsigned long slave_adr[2];
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unsigned long slave_trn[2];
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unsigned long slave_ctl;
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unsigned long mastr_adr[4];
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unsigned long mastr_trn;
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unsigned long mastr_att;
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unsigned long mastr_ctl;
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unsigned long dma_ctl_1;
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unsigned long dma_ctl_2;
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unsigned long dma_loc_cnt;
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unsigned long dma_vme_cnt;
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unsigned long dma_byte_cnt;
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unsigned long dma_adr_cnt;
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unsigned long dma_status;
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unsigned long to_ctl;
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unsigned long timer_cmp_1;
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unsigned long timer_cnt_1;
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unsigned long timer_cmp_2;
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unsigned long timer_cnt_2;
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unsigned long board_ctl;
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unsigned long prescaler_cnt;
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unsigned long intr_stat;
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unsigned long intr_ena;
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unsigned long intr_soft_set;
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unsigned long intr_clear;
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unsigned long intr_level[4];
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unsigned long vector_base;
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} lcsr_regs;
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/*
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* Base address of VMEchip2 LCSR
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* Not configurable on the MVME167.
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* XXX what about 162?
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*/
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#define lcsr ((lcsr_regs * const) 0xFFF40000)
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/*
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* Vector numbers for the interrupts from the VMEchip2. Use the values
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* "recommended" by Motorola.
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* See pages 2-70 to 2-92, and table 2-3.
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*/
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/* MIEN (Master Interrupt Enable) bit in LCSR 0xFFF40088. */
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#define MASK_INT 0x00800000
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/* The content of VBR0 corresponds to "X" in table 2-3 */
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#define VBR0 0x6
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/* The content of VBR1 corresponds to "Y" in table 2-3 */
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#define VBR1 0x7
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/*
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* Representation of the PCCchip2
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*/
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typedef volatile struct pccchip2_regs_ {
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unsigned char chip_id; /* 0xFFF42000 */
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unsigned char chip_revision; /* 0xFFF42001 */
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unsigned char gen_control; /* 0xFFF42002 */
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unsigned char vector_base; /* 0xFFF42003 */
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unsigned long timer_cmp_1; /* 0xFFF42004 */
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unsigned long timer_cnt_1; /* 0xFFF42008 */
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unsigned long timer_cmp_2; /* 0xFFF4200C */
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unsigned long timer_cnt_2; /* 0xFFF42010 */
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unsigned char LSB_prescaler_count;/* 0xFFF42014 */
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unsigned char prescaler_clock_adjust; /* 0xFFF42015 */
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unsigned char timer_ctl_2; /* 0xFFF42016 */
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unsigned char timer_ctl_1; /* 0xFFF42017 */
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unsigned char gpi_int_ctl; /* 0xFFF42018 */
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unsigned char gpio_ctl; /* 0xFFF42019 */
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unsigned char timer_int_ctl_2; /* 0xFFF4201A */
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unsigned char timer_int_ctl_1; /* 0xFFF4201B */
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unsigned char SCC_error; /* 0xFFF4201C */
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unsigned char SCC_modem_int_ctl; /* 0xFFF4201D */
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unsigned char SCC_tx_int_ctl; /* 0xFFF4201E */
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unsigned char SCC_rx_int_ctl; /* 0xFFF4201F */
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unsigned char reserved1[3];
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unsigned char modem_piack; /* 0xFFF42023 */
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unsigned char reserved2;
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unsigned char tx_piack; /* 0xFFF42025 */
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unsigned char reserved3;
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unsigned char rx_piack; /* 0xFFF42027 */
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unsigned char LANC_error; /* 0xFFF42028 */
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unsigned char reserved4;
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unsigned char LANC_int_ctl; /* 0xFFF4202A */
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unsigned char LANC_berr_ctl; /* 0xFFF4202B */
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unsigned char SCSI_error; /* 0xFFF4202C */
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unsigned char reserved5[2];
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unsigned char SCSI_int_ctl; /* 0xFFF4202F */
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unsigned char print_ack_int_ctl; /* 0xFFF42030 */
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unsigned char print_fault_int_ctl;/* 0xFFF42031 */
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unsigned char print_sel_int_ctl; /* 0xFFF42032 */
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unsigned char print_pe_int_ctl; /* 0xFFF42033 */
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unsigned char print_busy_int_ctl; /* 0xFFF42034 */
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unsigned char reserved6;
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unsigned char print_input_status; /* 0xFFF42036 */
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unsigned char print_ctl; /* 0xFFF42037 */
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unsigned char chip_speed; /* 0xFFF42038 */
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unsigned char reserved7;
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unsigned char print_data; /* 0xFFF4203A */
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unsigned char reserved8[3];
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unsigned char int_level; /* 0xFFF4203E */
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unsigned char int_mask; /* 0xFFF4203F */
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} pccchip2_regs;
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/*
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* Base address of the PCCchip2.
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* This is not configurable in the MVME167.
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*/
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#define pccchip2 ((pccchip2_regs * const) 0xFFF42000)
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/*
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* On the MVME162, we have the mcchip and the pccchip2 on
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* the 167. They are similar but different enough where
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* we have to reconcile them later.
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*/
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/*
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* Vector numbers for the interrupts from the PCCchip2. Use the values
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* "recommended" by Motorola.
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* See page 3-15.
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*/
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#define PCCCHIP2_VBR 0x5
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/*
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* The following registers are located in the VMEbus short
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* IO space and respond to address modifier codes $29 and $2D.
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* On FORCE CPU use address gcsr_vme and device /dev/vme16d32.
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*/
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typedef volatile struct {
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unsigned char chip_revision;
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unsigned char chip_id;
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unsigned char lmsig;
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unsigned char board_scr;
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unsigned short gpr[6];
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} gcsr_regs;
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#define gcsr_vme ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS))
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#define gcsr ((gcsr_regs * const) 0xFFF40100)
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/*
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* Representation of 82596CA LAN controller: Memory Map
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*/
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typedef volatile struct i82596_regs_ {
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unsigned short port_lower; /* 0xFFF46000 */
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unsigned short port_upper; /* 0xFFF46002 */
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unsigned long chan_attn; /* 0xFFF46004 */
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} i82596_regs;
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/*
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* Base address of the 82596.
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*/
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#define i82596 ((i82596_regs * const) 0xFFF46000)
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/*
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* Representation of initialization data in NVRAM
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*/
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#if defined(mvme167)
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typedef volatile struct nvram_config_ {
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unsigned char cache_mode; /* 0xFFFC0000 */
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unsigned char console_mode; /* 0xFFFC0001 */
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unsigned char console_printk_port; /* 0xFFFC0002 */
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unsigned char pad1; /* 0xFFFC0003 */
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unsigned long ipaddr; /* 0xFFFC0004 */
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unsigned long netmask; /* 0xFFFC0008 */
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unsigned char enaddr[6]; /* 0xFFFC000C */
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unsigned short processor_id; /* 0xFFFC0012 */
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unsigned long rma_start; /* 0xFFFC0014 */
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unsigned long vma_start; /* 0xFFFC0018 */
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unsigned long ramsize; /* 0xFFFC001C */
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} nvram_config;
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/*
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* Pointer to the base of User Area NVRAM
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*/
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#define nvram ((nvram_config * const) 0xFFFC0000)
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#endif
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/*
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* Flag to indicate if J1-4 is on (and parameters should be
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* sought in User Area NVRAM)
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*
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* NOTE: If NVRAM has bad settings, the you want to disable this
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* on the MVME167.
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*/
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#if defined(mvme167)
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#define NVRAM_CONFIGURE \
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( !( ( (unsigned char)(lcsr->vector_base & 0xFF) ) & 0x10 ) )
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#else
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#define NVRAM_CONFIGURE 0
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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