forked from Imagelibrary/rtems
a9e62c242f
* ep1a/irq/irq.c, gen5200/irq/irq.c, gen83xx/irq/irq_init.c, mbx8xx/irq/irq.c, mpc8260ads/irq/irq.c, mvme5500/irq/irq.c, psim/irq/no_pic.c, score603e/irq/irq.c, shared/irq/irq_supp.h, shared/irq/openpic_i8259_irq.c, virtex/irq/irq_init.c: let C_dispatch_irq_handler() return zero to indicate to low-level exception handling code that the exception was handled (not used yet).
688 lines
19 KiB
C
688 lines
19 KiB
C
/* irq.c
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*
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* This file contains the implementation of the function described in irq.h
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*
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* Copyright (C) 1998, 1999 valette@crf.canon.fr
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* Acknowledgement May 2004 : to Till Straumann <strauman@slac.stanford.edu>
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* for some inputs.
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*
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* Copyright 2003, 2004, 2005, 2007 Shuchen Kate Feng <feng1@bnl.gov>,
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* NSLS,Brookhaven National Laboratory
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* 1) Modified and added support for the MVME5500 board.
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* 2) The implementation of picIsrTable[] is an original work by the
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* author to optimize the software IRQ priority scheduling because
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* Discovery controller does not provide H/W IRQ priority schedule.
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* It ensures the fastest/faster interrupt service to the
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* highest/higher priority IRQ, if pendig.
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* 3) _CPU_MSR_SET() needs RTEMS_COMPILER_MEMORY_BARRIER()
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*
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*/
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#include <rtems/system.h>
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#include <bsp.h>
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#include <bsp/irq.h>
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#include <rtems/score/thread.h>
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#include <rtems/score/apiext.h>
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#include <libcpu/raw_exception.h>
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#include <rtems/rtems/intr.h>
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#include <libcpu/io.h>
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#include <libcpu/byteorder.h>
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#include <bsp/vectors.h>
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#include <rtems/bspIo.h> /* for printk */
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#include "bsp/gtreg.h"
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#define HI_INT_CAUSE 0x40000000
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#define MAX_IRQ_LOOP 30
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#define EDGE_TRIGGER
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#define _MSR_GET( _mask) \
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do { \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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_CPU_MSR_GET( _mask); \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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} while (0);
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#define _MSR_SET( _mask) \
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do { \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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_CPU_MSR_SET( _mask); \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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} while (0);
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/* #define DEBUG_IRQ*/
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/*
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* pointer to the mask representing the additionnal irq vectors
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* that must be disabled when a particular entry is activated.
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* They will be dynamically computed from the table given
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* in BSP_rtems_irq_mngt_set();
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* CAUTION : this table is accessed directly by interrupt routine
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* prologue.
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*/
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static unsigned int BSP_irq_prio_mask_tbl[3][BSP_PIC_IRQ_NUMBER];
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/*
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* default handler connected on each irq after bsp initialization
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*/
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static rtems_irq_connect_data default_rtems_entry;
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/*
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* location used to store initial tables used for interrupt
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* management.
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*/
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static rtems_irq_global_settings* internal_config;
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static rtems_irq_connect_data* rtems_hdl_tbl;
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static volatile unsigned *BSP_irqMask_reg[3];
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static volatile unsigned *BSP_irqCause_reg[3];
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static volatile unsigned BSP_irqMask_cache[3]={0,0,0};
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static int picIsrTblPtr=0;
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static unsigned int GPPIrqInTbl=0;
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static unsigned long long MainIrqInTbl=0;
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/*
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* The software developers are forbidden to setup picIsrTable[],
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* as it is a powerful engine for the BSP to find the pending
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* highest priority IRQ at run time. It ensures the fastest/faster
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* interrupt service to the highest/higher priority IRQ, if pendig.
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*
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* The picIsrTable[96] is updated dynamically at run time
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* based on the priority levels set at BSPirqPrioTable[96],
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* while the BSP_enable_pic_irq(), and BSP_disable_pic_irq()
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* commands are invoked.
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*
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* The picIsrTable[96] lists the enabled CPU main and GPP external interrupt
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* numbers [0 (lowest)- 95 (highest)] starting from the highest priority
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* one to the lowest priority one. The highest priority interrupt is
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* located at picIsrTable[0], and the lowest priority interrupt is located
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* at picIsrTable[picIsrTblPtr-1].
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*
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*
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*/
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/* BitNums for Main Interrupt Lo/High Cause and GPP, -1 means invalid bit */
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static unsigned int picIsrTable[BSP_PIC_IRQ_NUMBER]={
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1 };
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/*
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* Check if IRQ is a MAIN CPU internal IRQ or GPP external IRQ
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*/
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static inline int is_pic_irq(const rtems_irq_number irqLine)
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{
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return (((int) irqLine <= BSP_GPP_IRQ_MAX_OFFSET) &
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((int) irqLine >= BSP_MICL_IRQ_LOWEST_OFFSET)
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);
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}
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/*
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* Check if IRQ is a Porcessor IRQ
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*/
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static inline int is_processor_irq(const rtems_irq_number irqLine)
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{
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return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) &
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((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
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);
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}
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static inline unsigned int divIrq32(unsigned irq)
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{
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return(irq/32);
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}
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static inline unsigned int modIrq32(unsigned irq)
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{
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return(irq%32);
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}
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/*
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* ------------------------ RTEMS Irq helper functions ----------------
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*/
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/*
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* Caution : this function assumes the variable "internal_config"
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* is already set and that the tables it contains are still valid
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* and accessible.
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*/
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static void compute_pic_masks_from_prio()
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{
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int i,j, k;
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unsigned long long irq_prio_mask=0;
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/*
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* Always mask at least current interrupt to prevent re-entrance
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*/
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for (i=0; i <BSP_PIC_IRQ_NUMBER; i++) {
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switch(i) {
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case BSP_MAIN_GPP7_0_IRQ:
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case BSP_MAIN_GPP15_8_IRQ:
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case BSP_MAIN_GPP23_16_IRQ:
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case BSP_MAIN_GPP31_24_IRQ:
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for (k=0; k< 3; k++)
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BSP_irq_prio_mask_tbl[k][i]=0;
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irq_prio_mask =0;
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break;
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default :
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irq_prio_mask = (unsigned long long) (1LLU << i);
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break;
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}
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if (irq_prio_mask) {
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for (j = 0; j <BSP_MAIN_IRQ_NUMBER; j++) {
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/*
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* Mask interrupts at PIC level that have a lower priority
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* or <Till Straumann> a equal priority.
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*/
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if (internal_config->irqPrioTbl [i] >= internal_config->irqPrioTbl [j])
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irq_prio_mask |= (unsigned long long)(1LLU << j);
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}
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BSP_irq_prio_mask_tbl[0][i] = irq_prio_mask & 0xffffffff;
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BSP_irq_prio_mask_tbl[1][i] = (irq_prio_mask>>32) & 0xffffffff;
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#ifdef DEBUG
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printk("irq_mask_prio_tbl[%d]:0x%8x%8x\n",i,BSP_irq_prio_mask_tbl[1][i],
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BSP_irq_prio_mask_tbl[0][i]);
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#endif
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BSP_irq_prio_mask_tbl[2][i] = 1<<i;
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/* Compute for the GPP priority interrupt mask */
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for (j=BSP_GPP_IRQ_LOWEST_OFFSET; j <BSP_PROCESSOR_IRQ_LOWEST_OFFSET; j++) {
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if (internal_config->irqPrioTbl [i] >= internal_config->irqPrioTbl [j])
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BSP_irq_prio_mask_tbl[2][i] |= 1 << (j-BSP_GPP_IRQ_LOWEST_OFFSET);
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}
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}
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}
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}
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static void UpdateMainIrqTbl(int irqNum)
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{
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int i=0, j, shifted=0;
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switch (irqNum) {
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case BSP_MAIN_GPP7_0_IRQ:
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case BSP_MAIN_GPP15_8_IRQ:
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case BSP_MAIN_GPP23_16_IRQ:
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case BSP_MAIN_GPP31_24_IRQ:
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return; /* Do nothing, let GPP take care of it */
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break;
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}
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#ifdef SHOW_MORE_INIT_SETTINGS
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unsigned long val2, val1;
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#endif
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/* If entry not in table*/
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if ( ((irqNum<BSP_GPP_IRQ_LOWEST_OFFSET) &&
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(!((unsigned long long)(1LLU << irqNum) & MainIrqInTbl))) ||
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((irqNum>BSP_MICH_IRQ_MAX_OFFSET) &&
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(!(( 1 << (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)) & GPPIrqInTbl))))
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{
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while ( picIsrTable[i]!=-1) {
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if (internal_config->irqPrioTbl[irqNum]>internal_config->irqPrioTbl[picIsrTable[i]]) {
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/* all other lower priority entries shifted right */
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for (j=picIsrTblPtr;j>i; j--)
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picIsrTable[j]=picIsrTable[j-1];
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picIsrTable[i]=irqNum;
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shifted=1;
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break;
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}
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i++;
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}
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if (!shifted) picIsrTable[picIsrTblPtr]=irqNum;
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if (irqNum >BSP_MICH_IRQ_MAX_OFFSET)
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GPPIrqInTbl |= (1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET));
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else
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MainIrqInTbl |= (unsigned long long)(1LLU << irqNum);
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picIsrTblPtr++;
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}
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#ifdef SHOW_MORE_INIT_SETTINGS
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val2 = (MainIrqInTbl>>32) & 0xffffffff;
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val1 = MainIrqInTbl&0xffffffff;
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printk("irqNum %d, MainIrqInTbl 0x%x%x\n", irqNum, val2, val1);
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BSP_printPicIsrTbl();
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#endif
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}
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static void CleanMainIrqTbl(int irqNum)
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{
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int i, j;
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switch (irqNum) {
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case BSP_MAIN_GPP7_0_IRQ:
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case BSP_MAIN_GPP15_8_IRQ:
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case BSP_MAIN_GPP23_16_IRQ:
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case BSP_MAIN_GPP31_24_IRQ:
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return; /* Do nothing, let GPP take care of it */
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break;
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}
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if ( ((irqNum<BSP_GPP_IRQ_LOWEST_OFFSET) &&
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((unsigned long long)(1LLU << irqNum) & MainIrqInTbl)) ||
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((irqNum>BSP_MICH_IRQ_MAX_OFFSET) &&
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(( 1 << (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)) & GPPIrqInTbl)))
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{ /* If entry in table*/
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for (i=0; i<64; i++) {
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if (picIsrTable[i]==irqNum) {/*remove it from the entry */
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/* all other lower priority entries shifted left */
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for (j=i;j<picIsrTblPtr; j++)
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picIsrTable[j]=picIsrTable[j+1];
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if (irqNum >BSP_MICH_IRQ_MAX_OFFSET)
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GPPIrqInTbl &= ~(1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET));
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else
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MainIrqInTbl &= ~(1LLU << irqNum);
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picIsrTblPtr--;
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break;
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}
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}
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}
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}
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void BSP_enable_pic_irq(const rtems_irq_number irqNum)
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{
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unsigned bitNum, regNum;
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unsigned int level;
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bitNum = modIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
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regNum = divIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
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rtems_interrupt_disable(level);
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UpdateMainIrqTbl((int) irqNum);
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BSP_irqMask_cache[regNum] |= (1 << bitNum);
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out_le32(BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]);
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while (in_le32(BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]);
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rtems_interrupt_enable(level);
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}
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void BSP_disable_pic_irq(const rtems_irq_number irqNum)
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{
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unsigned bitNum, regNum;
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unsigned int level;
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bitNum = modIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
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regNum = divIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
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rtems_interrupt_disable(level);
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CleanMainIrqTbl((int) irqNum);
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BSP_irqMask_cache[regNum] &= ~(1 << bitNum);
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out_le32(BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]);
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while (in_le32(BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]);
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rtems_interrupt_enable(level);
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}
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int BSP_setup_the_pic() /* adapt the same name as shared/irq */
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{
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int i;
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/* Get ready for discovery BSP */
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BSP_irqMask_reg[0]= (volatile unsigned int *) (GT64260_REG_BASE + GT_CPU_INT_MASK_LO);
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BSP_irqMask_reg[1]= (volatile unsigned int *) (GT64260_REG_BASE + GT_CPU_INT_MASK_HI);
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BSP_irqMask_reg[2]= (volatile unsigned int *) (GT64260_REG_BASE + GT_GPP_Interrupt_Mask);
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BSP_irqCause_reg[0]= (volatile unsigned int *) (GT64260_REG_BASE + GT_MAIN_INT_CAUSE_LO);
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BSP_irqCause_reg[1]= (volatile unsigned int *) (GT64260_REG_BASE + GT_MAIN_INT_CAUSE_HI);
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BSP_irqCause_reg[2]= (volatile unsigned int *) (GT64260_REG_BASE + GT_GPP_Interrupt_Cause);
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#ifdef EDGE_TRIGGER
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/* Page 401, Table 598:
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* Comm Unit Arbiter Control register :
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* bit 10:GPP interrupts as level sensitive(1) or edge sensitive(0).
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* We set the GPP interrupts to be edge sensitive.
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* MOTload default is set as level sensitive(1).
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*/
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outl((inl(GT_CommUnitArb_Ctrl)& (~(1<<10))), GT_CommUnitArb_Ctrl);
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#else
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outl((inl(GT_CommUnitArb_Ctrl)| (1<<10)), GT_CommUnitArb_Ctrl);
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#endif
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#if 0
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printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n",
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in_le32(BSP_irqMask_reg[0]),
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in_le32(BSP_irqCause_reg[0]));
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printk("BSP_irqMask_reg[1] = 0x%x, BSP_irqCause_reg[1] 0x%x\n",
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in_le32(BSP_irqMask_reg[1]),
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in_le32(BSP_irqCause_reg[1]));
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printk("BSP_irqMask_reg[2] = 0x%x, BSP_irqCause_reg[2] 0x%x\n",
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in_le32(BSP_irqMask_reg[2]),
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in_le32(BSP_irqCause_reg[2]));
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#endif
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/* Initialize the interrupt related GT64260 registers */
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for (i=0; i<3; i++) {
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out_le32(BSP_irqCause_reg[i], 0);
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out_le32(BSP_irqMask_reg[i], 0);
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}
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in_le32(BSP_irqMask_reg[2]);
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compute_pic_masks_from_prio();
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#if 0
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printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n",
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in_le32(BSP_irqMask_reg[0]),
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in_le32(BSP_irqCause_reg[0]));
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printk("BSP_irqMask_reg[1] = 0x%x, BSP_irqCause_reg[1] 0x%x\n",
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in_le32(BSP_irqMask_reg[1]),
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in_le32(BSP_irqCause_reg[1]));
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printk("BSP_irqMask_reg[2] = 0x%x, BSP_irqCause_reg[2] 0x%x\n",
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in_le32(BSP_irqMask_reg[2]),
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in_le32(BSP_irqCause_reg[2]));
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#endif
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/*
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*
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*/
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for (i=BSP_MICL_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET ; i++) {
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if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
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BSP_enable_pic_irq(i);
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if (rtems_hdl_tbl[i].on)
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rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
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}
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else {
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if (rtems_hdl_tbl[i].off)
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rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
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BSP_disable_pic_irq(i);
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}
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}
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return(1);
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}
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/*
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* This function check that the value given for the irq line
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* is valid.
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*/
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static int isValidInterrupt(int irq)
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{
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if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET))
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return 0;
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return 1;
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}
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/*
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* ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
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*/
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int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
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{
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unsigned int level;
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if (!isValidInterrupt(irq->name)) {
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printk("Invalid interrupt vector %d\n",irq->name);
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return 0;
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}
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/*
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* Check if default handler is actually connected. If not issue an error.
|
|
* You must first get the current handler via i386_get_current_idt_entry
|
|
* and then disconnect it using i386_delete_idt_entry.
|
|
* RATIONALE : to always have the same transition by forcing the user
|
|
* to get the previous handler before accepting to disconnect.
|
|
*/
|
|
rtems_interrupt_disable(level);
|
|
if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {
|
|
rtems_interrupt_enable(level);
|
|
printk("IRQ vector %d already connected\n",irq->name);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* store the data provided by user
|
|
*/
|
|
rtems_hdl_tbl[irq->name] = *irq;
|
|
#ifdef BSP_SHARED_HANDLER_SUPPORT
|
|
rtems_hdl_tbl[irq->name].next_handler = (void *)-1;
|
|
#endif
|
|
|
|
if (is_pic_irq(irq->name)) {
|
|
/*
|
|
* Enable PIC irq : Main Interrupt Cause Low and High & GPP external
|
|
*/
|
|
#ifdef DEBUG_IRQ
|
|
printk("PIC irq %d\n",irq->name);
|
|
#endif
|
|
BSP_enable_pic_irq(irq->name);
|
|
}
|
|
else {
|
|
if (is_processor_irq(irq->name)) {
|
|
/*
|
|
* Enable exception at processor level
|
|
*/
|
|
|
|
}
|
|
}
|
|
/*
|
|
* Enable interrupt on device
|
|
*/
|
|
if (irq->on)
|
|
irq->on(irq);
|
|
|
|
rtems_interrupt_enable(level);
|
|
|
|
return 1;
|
|
}
|
|
|
|
|
|
int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq)
|
|
{
|
|
if (!isValidInterrupt(irq->name)) {
|
|
return 0;
|
|
}
|
|
*irq = rtems_hdl_tbl[irq->name];
|
|
return 1;
|
|
}
|
|
|
|
int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
|
|
{
|
|
unsigned int level;
|
|
|
|
if (!isValidInterrupt(irq->name)) {
|
|
return 0;
|
|
}
|
|
/*
|
|
* Check if default handler is actually connected. If not issue an error.
|
|
* You must first get the current handler via i386_get_current_idt_entry
|
|
* and then disconnect it using i386_delete_idt_entry.
|
|
* RATIONALE : to always have the same transition by forcing the user
|
|
* to get the previous handler before accepting to disconnect.
|
|
*/
|
|
if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
|
|
return 0;
|
|
}
|
|
rtems_interrupt_disable(level);
|
|
|
|
/*
|
|
* disable PIC interrupt
|
|
*/
|
|
if (is_pic_irq(irq->name))
|
|
BSP_disable_pic_irq(irq->name);
|
|
else {
|
|
if (is_processor_irq(irq->name)) {
|
|
/*
|
|
* disable exception at processor level
|
|
*/
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Disable interrupt on device
|
|
*/
|
|
if (irq->off)
|
|
irq->off(irq);
|
|
|
|
/*
|
|
* restore the default irq value
|
|
*/
|
|
rtems_hdl_tbl[irq->name] = default_rtems_entry;
|
|
|
|
|
|
rtems_interrupt_enable(level);
|
|
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------
|
|
*/
|
|
|
|
int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
|
|
{
|
|
unsigned int level;
|
|
int i;
|
|
|
|
/*
|
|
* Store various code accelerators
|
|
*/
|
|
internal_config = config;
|
|
default_rtems_entry = config->defaultEntry;
|
|
rtems_hdl_tbl = config->irqHdlTbl;
|
|
|
|
rtems_interrupt_disable(level);
|
|
|
|
if ( !BSP_setup_the_pic() ) {
|
|
printk("PIC setup failed; leaving IRQs OFF\n");
|
|
return 0;
|
|
}
|
|
|
|
for (i= BSP_MAIN_GPP7_0_IRQ; i <= BSP_MAIN_GPP31_24_IRQ; i++)
|
|
BSP_enable_pic_irq(i);
|
|
|
|
rtems_interrupt_enable(level);
|
|
return 1;
|
|
}
|
|
|
|
int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)
|
|
{
|
|
*config = internal_config;
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* High level IRQ handler called from shared_raw_irq_code_entry
|
|
*/
|
|
|
|
int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
|
|
{
|
|
register unsigned msr, new_msr;
|
|
unsigned long irqCause[3]={0, 0,0};
|
|
register unsigned long selectCause;
|
|
unsigned oldMask[3]={0,0,0};
|
|
register unsigned i=0, j, irq=0, bitmask=0, group=0;
|
|
|
|
if (excNum == ASM_DEC_VECTOR) {
|
|
_MSR_GET(msr);
|
|
new_msr = msr | MSR_EE;
|
|
_MSR_SET(new_msr);
|
|
|
|
rtems_hdl_tbl[BSP_DECREMENTER].hdl(rtems_hdl_tbl[BSP_DECREMENTER].handle);
|
|
|
|
_MSR_SET(msr);
|
|
return 0;
|
|
|
|
}
|
|
|
|
for (j=0; j<3; j++ ) oldMask[j] = BSP_irqMask_cache[j];
|
|
|
|
if ((selectCause= in_le32((volatile unsigned *)0xf1000c70)) & HI_INT_CAUSE ){
|
|
irqCause[1] = (selectCause & BSP_irqMask_cache[1]);
|
|
irqCause[2] = in_le32(BSP_irqCause_reg[2]) & BSP_irqMask_cache[2];
|
|
}
|
|
else {
|
|
irqCause[0] = (selectCause & BSP_irqMask_cache[0]);
|
|
if ((irqCause[1] =(in_le32((volatile unsigned *)0xf1000c68)&BSP_irqMask_cache[1])))
|
|
irqCause[2] = in_le32(BSP_irqCause_reg[2]) & BSP_irqMask_cache[2];
|
|
}
|
|
|
|
while ((irq = picIsrTable[i++])!=-1)
|
|
{
|
|
if (irqCause[group=(irq/32)] && (irqCause[group]&(bitmask=(1<<(irq % 32))))) {
|
|
for (j=0; j<3; j++)
|
|
BSP_irqMask_cache[j] &= (~ BSP_irq_prio_mask_tbl[j][irq]);
|
|
|
|
RTEMS_COMPILER_MEMORY_BARRIER();
|
|
out_le32((volatile unsigned *)0xf1000c1c, BSP_irqMask_cache[0]);
|
|
out_le32((volatile unsigned *)0xf1000c6c, BSP_irqMask_cache[1]);
|
|
out_le32((volatile unsigned *)0xf100f10c, BSP_irqMask_cache[2]);
|
|
in_le32((volatile unsigned *)0xf100f10c);
|
|
|
|
#ifdef EDGE_TRIGGER
|
|
if (irq > BSP_MICH_IRQ_MAX_OFFSET)
|
|
out_le32(BSP_irqCause_reg[2], ~bitmask);/* Till Straumann: Ack the edge triggered GPP IRQ */
|
|
#endif
|
|
|
|
_MSR_GET(msr);
|
|
new_msr = msr | MSR_EE;
|
|
_MSR_SET(new_msr);
|
|
rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle);
|
|
_MSR_SET(msr);
|
|
|
|
for (j=0; j<3; j++ ) BSP_irqMask_cache[j] = oldMask[j];
|
|
break;
|
|
}
|
|
}
|
|
|
|
out_le32((volatile unsigned *)0xf1000c1c, oldMask[0]);
|
|
out_le32((volatile unsigned *)0xf1000c6c, oldMask[1]);
|
|
out_le32((volatile unsigned *)0xf100f10c, oldMask[2]);
|
|
in_le32((volatile unsigned *)0xf100f10c);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
|
|
{
|
|
/*
|
|
* Process pending signals that have not already been
|
|
* processed by _Thread_Displatch. This happens quite
|
|
* unfrequently : the ISR must have posted an action
|
|
* to the current running thread.
|
|
*/
|
|
if ( _Thread_Do_post_task_switch_extension ||
|
|
_Thread_Executing->do_post_task_switch_extension ) {
|
|
_Thread_Executing->do_post_task_switch_extension = FALSE;
|
|
_API_extensions_Run_postswitch();
|
|
}
|
|
/*
|
|
* I plan to process other thread related events here.
|
|
* This will include DEBUG session requested from keyboard...
|
|
*/
|
|
}
|
|
|
|
/* Only print part of the entries for now */
|
|
void BSP_printPicIsrTbl()
|
|
{
|
|
int i;
|
|
|
|
printk("picIsrTable[12]={");
|
|
for (i=0; i<12; i++)
|
|
printk("%d,", picIsrTable[i]);
|
|
printk("}\n");
|
|
|
|
printk("GPPIrqInTbl: 0x%x :\n", GPPIrqInTbl);
|
|
}
|