forked from Imagelibrary/rtems
134 lines
4.0 KiB
Plaintext
134 lines
4.0 KiB
Plaintext
#
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# $Id: README,v 1.3.1 Shuchen Kate Feng, NSLS, BNL (08/27/07)
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#
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Please reference README.booting for the boot/load process.
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For the priority setting of the Interrupt Requests (IRQs), please
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reference README.irq
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The BSP is built and tested on the 4.7.1 and 4.7.99.2 CVS RTEMS release.
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I believe in valuable real-time programming, where technical neatness,
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performance and truth are. I hope I still believe. Any suggestion,
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bug reports, or even bug fixes (great!) would be highly appreciated
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so that I still believe what I believe.
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ACKNOWLEDGEMENTS
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----------------
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Acknowledgements:
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Valuable information was obtained from the following:
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1) Marvell NDA document for the discovery system controller.
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Other related documents are listed at :
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http://www.aps.anl.gov/epics/meetings/2006-06/RTEMS_Primer_SIG/RTEMS_BSP_MVME5500.pdf
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2) netBSD: For the two NICS and some headers :
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Allegro Networks, Inc., Wasabi Systems, Inc.
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3) RTEMS: This BSP also builds on top of the work of others who have
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contributed to similar RTEMS powerpc shared and motorola_powerpc BSPs, most
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notably Eric Valette, Till Straumann (SVGM1 BSP, too), Eric Norum and others.
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LICENSE
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-------
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See ./LICENSE file.
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BSP NAME: mvme5500
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BOARD: MVME5500 by Motorola
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BUS: PCI
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CPU FAMILY: ppc
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CPU: MPC7455 @ 1GHZ
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COPROCESSORS: N/A
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MODE: 32/64 bit mode (support 32 bit for now)
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DEBUG MONITOR: MOTLoad
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SYSTEM CONTROLLER: GT64260B
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PERIPHERALS
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===========
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TIMERS: Eight, 32 bit programmable
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SERIAL PORTS: 2 NS 16550 on GT64260B
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REAL-TIME CLOCK: MK48T37V
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32K NVSRAM: MK48T37V
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WATCHDOG TIMER: use the one in GT-64260B
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DMA: 8 channel DMA controller (GT-64260B)
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VIDEO: none
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NETWORKING: Port 1: Intel 82544EI Gigabit Ethernet Controller
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10/100/1000Mb/s routed to front panel RJ-45
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Port 2: 10/100 Mb ethernet unit integrated on the
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Marvell's GT64260 system controller
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DRIVER INFORMATION
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==================
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CLOCK DRIVER: PPC internal
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IOSUPP DRIVER: N/A
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SHMSUPP: N/A
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TIMER DRIVER: PPC internal
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TTY DRIVER: PPC internal
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STDIO
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=====
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PORT: Console port 0
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ELECTRICAL: na
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BAUD: na
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BITS PER CHARACTER: na
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PARITY: na
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STOP BITS: na
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Jumpers
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=======
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1) The BSP is tested with the 60x bus mode instead of the MPX bus mode.
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( No jumper or a jumper across pins 1-2 on J19 selects the 60x bus mode)
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2) On the mvme5500 board, Ethernet 1 is the Gigabit Ethernet port and is
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front panel only. Ethernet 2 is 10/100 BaseT Ethernet. For front-panel
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Ethernet2, install jumpers across pins 1-2 on all J6, J7, J100 and
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J101 headers.
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3) Enable SROM initialization at startup. (No jumper or a jumper across
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pins 1-2 on J17)
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In fact, (if I did not miss anything) the mvme5500 board should function
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properly if one keeps all the jumpers at factory configuration.
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One can leave out the jumper on J30 to disable EEPROM programming.
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Notes
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=====
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BSP BAT usage
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----------------------
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DBAT0 and IBAT0
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0x00000000
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0x0fffffff 1st 256M, for MEMORY access (caching enabled)
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DBAT1 and IBAT1
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0x00000000
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0x0fffffff 2nd 256M, for MEMORY access (caching enabled)
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UPDATE: (2004/5).
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The BSP now uses page tables for mapping the entire 512MB
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of RAM. DBAT0 and DBAT1 is hence free for use by the
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application. A simple 1:1 (virt<->phys) mapping is employed.
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The BSP write-protects the text and read-only data
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areas of the application. Special acknowledgement to Till
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Straumann <strauman@slac.stanford.edu> for providing inputs in
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porting the memory protection software he wrote (BSP_pgtbl_xxx())
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to MVME5500.
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The default VME configuration uses DBAT0 to map
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more PCI memory space for use by the universe VME
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bridge:
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DBAT0
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0x90000000 PCI memory space <-> VME
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0x9fffffff
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Port VME-Addr Size PCI-Adrs Mode:
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0: 0x20000000 0x0F000000 0x90000000 A32, Dat, Sup
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1: 0x00000000 0x00FF0000 0x9F000000 A24, Dat, Sup
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2: 0x00000000 0x00010000 0x9FFF0000 A16, Dat, Sup
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