forked from Imagelibrary/rtems
523 lines
17 KiB
C
523 lines
17 KiB
C
/*
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* BSP startup
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*
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* This routine starts the application. It includes application,
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* board, and monitor specific initialization and configuration.
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* The generic CPU dependent initialization has been performed
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* before this routine is invoked.
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*
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* Author:
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* David Fiddes, D.J@fiddes.surfaid.org
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* http://www.calm.hw.ac.uk/davidf/coldfire/
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*
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* COPYRIGHT (c) 1989-1998.
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* On-Line Applications Research Corporation (OAR).
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* Copyright assigned to U.S. Government, 1994.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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*
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* http://www.OARcorp.com/rtems/license.html.
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*
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* $Id$
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*/
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#include <bsp.h>
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#include <rtems/libio.h>
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#include <rtems/libcsupport.h>
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#include <string.h>
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#include <errno.h>
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/*
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* The original table from the application and our copy of it with
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* some changes.
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*/
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extern rtems_configuration_table Configuration;
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rtems_configuration_table BSP_Configuration;
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rtems_cpu_table Cpu_table;
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char *rtems_progname;
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/*
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* Location of 'VME' access
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*/
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#define VME_ONE_BASE 0x30000000
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#define VME_TWO_BASE 0x31000000
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/*
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* CPU-space access
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* The NOP after writing the CACR is there to address the following issue as
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* described in "Device Errata MCF5282DE", Rev. 1.7, 09/2004:
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*
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* 6 Possible Cache Corruption after Setting CACR[CINV]
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* 6.1 Description
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* The cache on the MCF5282 was enhanced to function as a unified data and
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* instruction cache, an instruction cache, or an operand cache. The cache
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* function and organization is controlled by the cache control register (CACR).
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* The CINV (Bit 24 = cache invalidate) bit in the CACR causes a cache clear.
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* If the cache is configured as a unified cache and the CINV bit is set, the
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* scope of the cache clear is controlled by two other bits in the CACR,
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* INVI (BIT 21 = CINV instruction cache only) and INVD (BIT 20 = CINV data
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* cache only). These bits allow the entire cache, just the instruction
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* portion of the cache, or just the data portion of the cache to be cleared.
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* If a write to the CACR is performed to clear the cache (CINV = BIT 24 set)
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* and only a partial clear will be done (INVI = BIT 21 or INVD = BIT 20 set),
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* then cache corruption may occur.
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*
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* 6.2 Workaround
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* All loads of the CACR that perform a cache clear operation (CINV = BIT 24)
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* should be followed immediately by a NOP instruction. This avoids the cache
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* corruption problem.
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* DATECODES AFFECTED: All
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*/
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#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr ; nop" : : "d" (_cacr))
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#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
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#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
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/*
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* Read/write copy of common cache
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* Split I/D cache
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* Allow CPUSHL to invalidate a cache line
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* Enable buffered writes
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* No burst transfers on non-cacheable accesses
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* Default cache mode is *disabled* (cache only ACRx areas)
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*/
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static uint32_t cacr_mode = MCF5XXX_CACR_CENB |
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MCF5XXX_CACR_DBWE |
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MCF5XXX_CACR_DCM;
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/*
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* Cannot be frozen
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*/
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void _CPU_cache_freeze_data(void) {}
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void _CPU_cache_unfreeze_data(void) {}
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void _CPU_cache_freeze_instruction(void) {}
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void _CPU_cache_unfreeze_instruction(void) {}
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/*
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* Write-through data cache -- flushes are unnecessary
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*/
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void _CPU_cache_flush_1_data_line(const void *d_addr) {}
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void _CPU_cache_flush_entire_data(void) {}
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void _CPU_cache_enable_instruction(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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cacr_mode &= ~MCF5XXX_CACR_DIDI;
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m68k_set_cacr(cacr_mode);
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rtems_interrupt_enable(level);
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}
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void _CPU_cache_disable_instruction(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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cacr_mode |= MCF5XXX_CACR_DIDI;
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m68k_set_cacr(cacr_mode);
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rtems_interrupt_enable(level);
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}
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void _CPU_cache_invalidate_entire_instruction(void)
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{
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m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
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}
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void _CPU_cache_invalidate_1_instruction_line(const void *addr)
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{
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/*
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* Top half of cache is I-space
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*/
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addr = (void *)((int)addr | 0x400);
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asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
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}
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void _CPU_cache_enable_data(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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cacr_mode &= ~MCF5XXX_CACR_DISD;
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m68k_set_cacr(cacr_mode);
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rtems_interrupt_enable(level);
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}
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void _CPU_cache_disable_data(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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rtems_interrupt_disable(level);
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cacr_mode |= MCF5XXX_CACR_DISD;
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m68k_set_cacr(cacr_mode);
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rtems_interrupt_enable(level);
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}
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void _CPU_cache_invalidate_entire_data(void)
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{
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m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
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}
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void _CPU_cache_invalidate_1_data_line(const void *addr)
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{
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/*
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* Bottom half of cache is D-space
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*/
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addr = (void *)((int)addr & ~0x400);
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asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
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}
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/*
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* Use the shared implementations of the following routines
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*/
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void bsp_postdriver_hook(void);
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void bsp_libc_init( void *, uint32_t, int );
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void bsp_pretasking_hook(void); /* m68k version */
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/*
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* bsp_start
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*
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* This routine does the bulk of the system initialisation.
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*/
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void bsp_start( void )
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{
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extern char _WorkspaceBase[];
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extern char _RamBase[], _RamSize[];
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extern unsigned long _M68k_Ramsize;
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_M68k_Ramsize = (unsigned long)_RamSize; /* RAM size set in linker script */
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/*
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* Allocate the memory for the RTEMS Work Space. This can come from
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* a variety of places: hard coded address, malloc'ed from outside
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* RTEMS world (e.g. simulator or primitive memory manager), or (as
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* typically done by stock BSPs) by subtracting the required amount
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* of work space from the last physical address on the CPU board.
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*/
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/*
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* Need to "allocate" the memory for the RTEMS Workspace and
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* tell the RTEMS configuration where it is. This memory is
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* not malloc'ed. It is just "pulled from the air".
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*/
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BSP_Configuration.work_space_start = (void *)_WorkspaceBase;
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/*
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* initialize the CPU table for this BSP
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*/
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Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */
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Cpu_table.postdriver_hook = bsp_postdriver_hook;
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Cpu_table.do_zero_of_workspace = TRUE;
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Cpu_table.interrupt_stack_size = 4096;
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Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */
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/*
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* Invalidate the cache and disable it
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*/
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m68k_set_acr0(0);
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m68k_set_acr1(0);
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m68k_set_cacr(MCF5XXX_CACR_CINV);
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/*
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* Cache SDRAM
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*/
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m68k_set_acr0(MCF5XXX_ACR_AB((uint32_t)_RamBase) |
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MCF5XXX_ACR_AM((uint32_t)_RamSize-1) |
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MCF5XXX_ACR_EN |
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MCF5XXX_ACR_BWE |
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MCF5XXX_ACR_SM_IGNORE);
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/*
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* Enable the cache
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*/
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m68k_set_cacr(cacr_mode);
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/*
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* Set up CS* space (fake 'VME')
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* Two A24/D16 spaces, supervisor data acces
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*/
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MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE);
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MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M |
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MCF5282_CS_CSMR_CI |
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MCF5282_CS_CSMR_SC |
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MCF5282_CS_CSMR_UC |
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MCF5282_CS_CSMR_UD |
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MCF5282_CS_CSMR_V;
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MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16;
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MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE);
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MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M |
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MCF5282_CS_CSMR_CI |
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MCF5282_CS_CSMR_SC |
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MCF5282_CS_CSMR_UC |
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MCF5282_CS_CSMR_UD |
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MCF5282_CS_CSMR_V;
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MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16;
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}
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uint32_t bsp_get_CPU_clock_speed(void)
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{
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extern char _CPUClockSpeed[];
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return( (uint32_t)_CPUClockSpeed);
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}
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/*
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* Interrupt controller allocation
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*/
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rtems_status_code
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bsp_allocate_interrupt(int level, int priority)
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{
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static char used[7];
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rtems_interrupt_level l;
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rtems_status_code ret = RTEMS_RESOURCE_IN_USE;
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if ((level < 1) || (level > 7) || (priority < 0) || (priority > 7))
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return RTEMS_INVALID_NUMBER;
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rtems_interrupt_disable(l);
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if ((used[level-1] & (1 << priority)) == 0) {
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used[level-1] |= (1 << priority);
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ret = RTEMS_SUCCESSFUL;
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}
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rtems_interrupt_enable(l);
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return ret;
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}
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/*
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* Arcturus bootloader system calls
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*/
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#define syscall_return(type, ret) \
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do { \
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if ((unsigned long)(ret) >= (unsigned long)(-64)) { \
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errno = -(ret); \
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ret = -1; \
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} \
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return (type)(ret); \
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} while (0)
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#define syscall_1(type,name,d1type,d1) \
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type bsp_##name(d1type d1) \
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{ \
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long ret; \
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register long __d1 __asm__ ("%d1") = (long)d1; \
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__asm__ __volatile__ ("move.l %1,%%d0\n\t" \
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"trap #2\n\t" \
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"move.l %%d0,%0" \
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: "=g" (ret) \
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: "i" (SysCode_##name), "d" (__d1) \
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: "d0" ); \
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syscall_return(type,ret); \
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}
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#define syscall_2(type,name,d1type,d1,d2type,d2) \
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type bsp_##name(d1type d1, d2type d2) \
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{ \
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long ret; \
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register long __d1 __asm__ ("%d1") = (long)d1; \
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register long __d2 __asm__ ("%d2") = (long)d2; \
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__asm__ __volatile__ ("move.l %1,%%d0\n\t" \
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"trap #2\n\t" \
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"move.l %%d0,%0" \
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: "=g" (ret) \
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: "i" (SysCode_##name), "d" (__d1),\
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"d" (__d2) \
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: "d0" ); \
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syscall_return(type,ret); \
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}
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#define syscall_3(type,name,d1type,d1,d2type,d2,d3type,d3) \
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type bsp_##name(d1type d1, d2type d2, d3type d3) \
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{ \
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long ret; \
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register long __d1 __asm__ ("%d1") = (long)d1; \
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register long __d2 __asm__ ("%d2") = (long)d2; \
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register long __d3 __asm__ ("%d3") = (long)d3; \
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__asm__ __volatile__ ("move.l %1,%%d0\n\t" \
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"trap #2\n\t" \
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"move.l %%d0,%0" \
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: "=g" (ret) \
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: "i" (SysCode_##name), "d" (__d1),\
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"d" (__d2),\
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"d" (__d3) \
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: "d0" ); \
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syscall_return(type,ret); \
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}
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#define SysCode_reset 0 /* reset */
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#define SysCode_program 5 /* program flash memory */
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#define SysCode_gethwaddr 12 /* get hardware address */
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#define SysCode_getbenv 14 /* get bootloader environment variable */
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#define SysCode_setbenv 15 /* get bootloader environment variable */
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#define SysCode_flash_erase_range 19 /* erase a section of flash */
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#define SysCode_flash_write_range 20 /* write a section of flash */
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syscall_1(unsigned const char *, gethwaddr, int, a)
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syscall_1(const char *, getbenv, const char *, a)
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syscall_2(int, program, bsp_mnode_t *, chain, int, flags)
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syscall_3(int, flash_erase_range, volatile unsigned short *, flashptr, int, start, int, end);
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syscall_3(int, flash_write_range, volatile unsigned short *, flashptr, bsp_mnode_t *, chain, int, offset);
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/*
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* 'Extended BSP' routines
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* Should move to cpukit/score/cpu/m68k/cpu.c someday.
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*/
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rtems_status_code bspExtInit(void) { return RTEMS_SUCCESSFUL; }
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int BSP_enableVME_int_lvl(unsigned int level) { return 0; }
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int BSP_disableVME_int_lvl(unsigned int level) { return 0; }
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/*
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* 'VME' interrupt support
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* Interrupt vectors 192-255 are set aside for use by external logic
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* which drives IRQ1*. The actual interrupt source is read from the
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* external logic at FPGA_IRQ_INFO. The most-significant bit of the
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* value read from this location is set as long as the external logic
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* has interrupts to be serviced. The least-significant six bits
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* indicate the interrupt source within the external logic and are used
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* to select the specified interupt handler.
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*/
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#define NVECTOR 256
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#define FPGA_VECTOR (64+1) /* IRQ1* pin connected to external FPGA */
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#define FPGA_EPPAR MCF5282_EPORT_EPPAR_EPPA1_BOTHEDGE
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#define FPGA_EPDDR MCF5282_EPORT_EPDDR_EPDD1
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#define FPGA_EPIER MCF5282_EPORT_EPIER_EPIE1
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#define FPGA_EPPDR MCF5282_EPORT_EPPDR_EPPD1
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#define FPGA_IRQ_INFO *((vuint16 *)(0x31000000 + 0xfffffe))
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static struct handlerTab {
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BSP_VME_ISR_t func;
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void *arg;
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} handlerTab[NVECTOR];
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BSP_VME_ISR_t
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BSP_getVME_isr(unsigned long vector, void **pusrArg)
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{
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if (vector >= NVECTOR)
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return (BSP_VME_ISR_t)NULL;
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if (pusrArg)
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*pusrArg = handlerTab[vector].arg;
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return handlerTab[vector].func;
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}
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static rtems_isr
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trampoline (rtems_vector_number v)
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{
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/*
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* Handle FPGA interrupts until all have been consumed
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*/
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if (v == FPGA_VECTOR) {
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while (((MCF5282_EPORT_EPPDR & FPGA_EPPDR) == 0)
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&& ((v = FPGA_IRQ_INFO) & 0x80)) {
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v = 192 + (v & 0x3f);
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if (handlerTab[v].func)
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(*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
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else
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rtems_fatal_error_occurred(v);
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}
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}
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else if (handlerTab[v].func)
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(*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
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}
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int
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BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
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{
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rtems_isr_entry old_handler;
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rtems_interrupt_level level;
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/*
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* Register the handler information
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*/
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if (vector >= NVECTOR)
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return -1;
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handlerTab[vector].func = handler;
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handlerTab[vector].arg = usrArg;
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/*
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* If this is an external FPGA ('VME') vector set up the real IRQ.
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*/
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if ((vector >= 192) && (vector <= 255)) {
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int i;
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static volatile int setupDone;
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rtems_interrupt_disable(level);
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if (setupDone) {
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rtems_interrupt_enable(level);
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return 0;
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}
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MCF5282_EPORT_EPPAR &= ~FPGA_EPPAR;
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MCF5282_EPORT_EPDDR &= ~FPGA_EPDDR;
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MCF5282_EPORT_EPIER |= FPGA_EPIER;
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setupDone = 1;
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i = BSP_installVME_isr(FPGA_VECTOR, NULL, NULL);
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rtems_interrupt_enable(level);
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return i;
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}
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/*
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* Make the connection between the interrupt and the local handler
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*/
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rtems_interrupt_catch(trampoline, vector, &old_handler);
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/*
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* Find an unused level/priority if this is an on-chip (INTC0)
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* source and this is the first time the source is being used.
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* Interrupt sources 1 through 7 are fixed level/priority
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*/
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if ((vector >= 65) && (vector <= 127)) {
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int l, p;
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int source = vector - 64;
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static unsigned char installed[8];
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rtems_interrupt_disable(level);
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if (installed[source/8] & (1 << (source % 8))) {
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rtems_interrupt_enable(level);
|
|
return 0;
|
|
}
|
|
installed[source/8] |= (1 << (source % 8));
|
|
rtems_interrupt_enable(level);
|
|
for (l = 1 ; l < 7 ; l++) {
|
|
for (p = 0 ; p < 8 ; p++) {
|
|
if ((source < 8)
|
|
|| (bsp_allocate_interrupt(l,p) == RTEMS_SUCCESSFUL)) {
|
|
if (source >= 8)
|
|
*(&MCF5282_INTC0_ICR1 + (source - 1)) =
|
|
MCF5282_INTC_ICR_IL(l) |
|
|
MCF5282_INTC_ICR_IP(p);
|
|
rtems_interrupt_disable(level);
|
|
if (source >= 32)
|
|
MCF5282_INTC0_IMRH &= ~(1 << (source - 32));
|
|
else
|
|
MCF5282_INTC0_IMRL &= ~((1 << source) |
|
|
MCF5282_INTC_IMRL_MASKALL);
|
|
rtems_interrupt_enable(level);
|
|
return 0;
|
|
}
|
|
}
|
|
}
|
|
return -1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
|
|
{
|
|
if (vector >= NVECTOR)
|
|
return -1;
|
|
if ((handlerTab[vector].func != handler)
|
|
|| (handlerTab[vector].arg != usrArg))
|
|
return -1;
|
|
handlerTab[vector].func = (BSP_VME_ISR_t)NULL;
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr)
|
|
{
|
|
unsigned long offset;
|
|
|
|
switch (am) {
|
|
default: return -1;
|
|
case VME_AM_SUP_SHORT_IO: offset = 0x31FF0000; break; /* A16/D16 */
|
|
case VME_AM_STD_SUP_DATA: offset = 0x30000000; break; /* A24/D16 */
|
|
case VME_AM_EXT_SUP_DATA: offset = 0x31000000; break; /* A32/D32 */
|
|
}
|
|
*plocaladdr = vmeaddr + offset;
|
|
return 0;
|
|
}
|