forked from Imagelibrary/rtems
94 lines
3.9 KiB
C
94 lines
3.9 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Copyright (C) 2021 Jan Sommer, German Aerospace Center (DLR)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H
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#define LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H
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#include <bsp/utility.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct {
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uint32_t config;
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#define CADENCE_SPI_CONFIG_MODEFAIL_EN BSP_BIT32(17)
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#define CADENCE_SPI_CONFIG_MANSTRT BSP_BIT32(16)
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#define CADENCE_SPI_CONFIG_MANSTRT_EN BSP_BIT32(15)
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#define CADENCE_SPI_CONFIG_MANUAL_CS BSP_BIT32(14)
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#define CADENCE_SPI_CONFIG_CS(val) BSP_FLD32(val, 10, 13)
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#define CADENCE_SPI_CONFIG_CS_GET(reg) BSP_FLD32GET(reg, 10, 13)
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#define CADENCE_SPI_CONFIG_CS_SET(reg, val) BSP_FLD32SET(reg, val, 10, 13)
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#define CADENCE_SPI_CONFIG_PERI_SEL BSP_BIT32(9)
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#define CADENCE_SPI_CONFIG_REF_CLK BSP_BIT32(8)
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#define CADENCE_SPI_CONFIG_BAUD_DIV(val) BSP_FLD32(val, 3, 5)
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#define CADENCE_SPI_CONFIG_BAUD_DIV_GET(reg) BSP_FLD32GET(reg, 3, 5)
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#define CADENCE_SPI_CONFIG_BAUD_DIV_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
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#define CADENCE_SPI_CONFIG_CLK_PH BSP_BIT32(2)
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#define CADENCE_SPI_CONFIG_CLK_POL BSP_BIT32(1)
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#define CADENCE_SPI_CONFIG_MSTREN BSP_BIT32(0)
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uint32_t irqstatus;
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uint32_t irqenable;
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uint32_t irqdisable;
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uint32_t irqmask;
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#define CADENCE_SPI_IXR_TXUF BSP_BIT32(6)
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#define CADENCE_SPI_IXR_RXFULL BSP_BIT32(5)
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#define CADENCE_SPI_IXR_RXNEMPTY BSP_BIT32(4)
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#define CADENCE_SPI_IXR_TXFULL BSP_BIT32(3)
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#define CADENCE_SPI_IXR_TXOW BSP_BIT32(2)
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#define CADENCE_SPI_IXR_MODF BSP_BIT32(1)
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#define CADENCE_SPI_IXR_RXOVR BSP_BIT32(0)
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uint32_t spienable;
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#define CADENCE_SPI_EN BSP_BIT32(0)
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uint32_t delay;
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#define CADENCE_SPI_DELAY_DNSS(val) BSP_FLD32(val, 24, 31)
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#define CADENCE_SPI_DELAY_DNSS_GET(reg) BSP_FLD32GET(reg, 24, 31)
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#define CADENCE_SPI_DELAY_DNSS_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
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#define CADENCE_SPI_DELAY_DBTWN(val) BSP_FLD32(val, 16, 23)
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#define CADENCE_SPI_DELAY_DBTWN_GET(reg) BSP_FLD32GET(reg, 16, 23)
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#define CADENCE_SPI_DELAY_DBTWN_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
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#define CADENCE_SPI_DELAY_DAFTER(val) BSP_FLD32(val, 8, 15)
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#define CADENCE_SPI_DELAY_DAFTER_GET(reg) BSP_FLD32GET(reg, 8, 15)
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#define CADENCE_SPI_DELAY_DAFTER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
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#define CADENCE_SPI_DELAY_DINT(val) BSP_FLD32(val, 0, 7)
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#define CADENCE_SPI_DELAY_DINT_GET(reg) BSP_FLD32GET(reg, 0, 7)
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#define CADENCE_SPI_DELAY_DINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
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uint32_t txdata;
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uint32_t rxdata;
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uint32_t slave_idle_count;
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uint32_t txthreshold;
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uint32_t rxthreshold;
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uint32_t unused[51];
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uint32_t moduleid;
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} cadence_spi;
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#ifdef __cplusplus
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}
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#endif
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#endif /* LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H */
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