forked from Imagelibrary/rtems
a78d31de7f
Remove copyright from DornerWorks since the files contain not contributions from this company. Fix the copyright years of the embedded brains contributions.
153 lines
6.1 KiB
C
153 lines
6.1 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSBSPsARMZynqMPRPU
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*
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* @brief This source file contains the implementation of
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* zynqmp_setup_mpu_and_cache().
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*/
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/*
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* Copyright (C) 2023 Reflex Aerospace GmbH
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*
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* Written by Philip Kirkpatrick <p.kirkpatrick@reflexaerospace.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <bsp.h>
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#include <bsp/start.h>
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#include <xil_mpu.h>
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#include <xil_cache.h>
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#include <xreg_cortexr5.h>
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static BSP_START_TEXT_SECTION void zynqmp_configure_mpu_sections(void);
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/*
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* Make weak and let the user override.
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*/
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BSP_START_TEXT_SECTION void zynqmp_setup_mpu_and_cache(void) __attribute__ ((weak));
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BSP_START_TEXT_SECTION void zynqmp_setup_mpu_and_cache(void)
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{
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zynqmp_configure_mpu_sections();
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Xil_EnableMPU();
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Xil_DCacheEnable();
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Xil_ICacheEnable();
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}
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/*
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* Setup MPU sections.
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*
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* The MPU on the ZynqMP RPU only supports 16 regions.
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* Regions must align on boundaries equal to the size of the region
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* Regions may overlap or be nested with the later definition taking precedence
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*
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* Note: LWIP for Zynq requires an available region in xemacpsif_dma.c:init_dma()
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* this is used for the BD memory.
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*
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* The following code attempts to implement the section map from Init_MPU() in
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* https://github.com/Xilinx/embeddedsw/blob/master/lib/bsp/standalone/src/arm/cortexr5/platform/ZynqMP/mpu.c
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* and from ARMV7_CP15_START_DEFAULT_SECTIONS in bsps/arm/include/bsp/arm-cp15-start.h
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* Due to the limitation on number of regions, some compromises have been made.
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* - Merges device memories instead of configuring each one independently
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* - For DRAM, assumes a baseline of `Normal write-back Cacheable` `Full Access`
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* then uses precedence to set no-cache and RO sections
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*
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* Reference:
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* https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/System-Address-Map-Interconnects
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* https://developer.arm.com/documentation/ddi0460/c/Memory-Protection-Unit
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*
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*| | Memory Range | Attributes of MPURegion |
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*|-----------------|-------------------------|-----------------------------|
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*| DDR | 0x00000000 - 0x7FFFFFFF | Normal write-back Cacheable |
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*| -rodata | | + PRIV_RO_USER_RO |
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*| -nocache | | Normal non-cacheable |
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*| -nocachenoload | | Normal non-cacheable |
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*| PL | 0x80000000 - 0xBFFFFFFF | Strongly Ordered |
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*| Devices | 0xC0000000 - 0xFFFFFFFF | Device Memory |
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*| -QSPI | 0xC0000000 - 0xDFFFFFFF | |
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*| -PCIe | 0xE0000000 - 0xEFFFFFFF | |
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*| -Reserved | 0xF0000000 - 0xF7FFFFFF | |
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*| -STM_CORESIGHT | 0xF8000000 - 0xF8FFFFFF | |
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*| -RPU_R5_GIC | 0xF9000000 - 0xF90FFFFF | |
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*| -Reserved | 0xF9100000 - 0xFCFFFFFF | |
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*| -FPS | 0xFD000000 - 0xFDFFFFFF | |
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*| -LPS | 0xFE000000 - 0xFFFFFFFF | (1) |
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*| OCM | 0xFFFC0000 - 0xFFFFFFFF | Normal write-back Cacheable |
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*
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* Note 1: Actual range for LPS goes to 0xFFBFFFFF, to use less sections go to
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* 0xFFFFFFFF and use precedence to configure OCM
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*/
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static BSP_START_TEXT_SECTION void zynqmp_configure_mpu_sections(void)
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{
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u32 addr;
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u64 size;
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u32 attrib;
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// Configure baseline DDR memory 0x00000000 - 0x7FFFFFFF
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addr = 0x00000000U;
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size = 0x80000000U;
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attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW;
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Xil_SetMPURegion(addr, size, attrib);
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// Configure PL interfaces 0x80000000 - 0xBFFFFFFF
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addr = 0x80000000U;
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size = 0x40000000U;
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attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW;
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Xil_SetMPURegion(addr, size, attrib);
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// Configure devices 0xC0000000 - 0xFFFFFFFF
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addr = 0xC0000000U;
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size = 0x40000000U;
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attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW;
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Xil_SetMPURegion(addr, size, attrib);
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// Configure OCM 0xFFFC0000 - 0xFFFFFFFF
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addr = 0xFFFC0000U;
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size = 0x00040000U;
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attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW;
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Xil_SetMPURegion(addr, size, attrib);
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// Add RO region for RO section
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addr = (u32) bsp_section_rodata_begin;
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size = bsp_section_rodata_end - bsp_section_rodata_begin;
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attrib = NORM_NSHARED_WB_WA | PRIV_RO_USER_RO;
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Xil_SetMPURegion(addr, size, attrib);
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// Add no cache region for no cache section
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addr = (u32) bsp_section_nocache_begin;
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size = bsp_section_nocache_end - bsp_section_nocache_begin;
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attrib = NORM_SHARED_NCACHE | PRIV_RW_USER_RW;
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Xil_SetMPURegion(addr, size, attrib);
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// Add no cache region for no cache no load section
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addr = (u32) bsp_section_nocachenoload_begin;
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size = bsp_section_nocachenoload_end - bsp_section_nocachenoload_begin;
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attrib = NORM_SHARED_NCACHE | PRIV_RW_USER_RW;
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Xil_SetMPURegion(addr, size, attrib);
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}
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