forked from Imagelibrary/rtems
5c30e3d376
Avoid using set_vector() which depends on _ISR_Vector_table(). Prepare for a statically initialized trap table. Update #4458.
100 lines
2.1 KiB
C
100 lines
2.1 KiB
C
/**
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* @file
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* @ingroup sparc_erc32
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* @brief Implementations for interrupt mechanisms for Time Test 27
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*/
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/*
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* COPYRIGHT (c) 2006.
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* Aeroflex Gaisler AB.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef _RTEMS_TMTEST27
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#error "This is an RTEMS internal file you must not include directly."
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#endif
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#ifndef __tm27_h
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#define __tm27_h
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/*
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* Define the interrupt mechanism for Time Test 27
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*
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* NOTE: Since the interrupt code for the SPARC supports both synchronous
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* and asynchronous trap handlers, support for testing with both
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* is included.
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*/
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#define ERC32_BSP_USE_SYNCHRONOUS_TRAP 0
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/*
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* The synchronous trap is an arbitrarily chosen software trap.
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*/
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#if (ERC32_BSP_USE_SYNCHRONOUS_TRAP == 1)
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#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 )
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#define MUST_WAIT_FOR_INTERRUPT 1
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#define Install_tm27_vector( handler ) \
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set_vector( (handler), TEST_VECTOR, 1 );
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#define Cause_tm27_intr() \
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__asm__ volatile( "ta 0x10; nop " );
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#define Clear_tm27_intr() /* empty */
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#define Lower_tm27_intr() /* empty */
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/*
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* The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.
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*/
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#else /* use a regular asynchronous trap */
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#define TEST_INTERRUPT_SOURCE ERC32_INTERRUPT_EXTERNAL_1
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#define TEST_INTERRUPT_SOURCE2 (ERC32_INTERRUPT_EXTERNAL_1+1)
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#define MUST_WAIT_FOR_INTERRUPT 1
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static inline void Install_tm27_vector(
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void ( *handler )( rtems_vector_number )
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)
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{
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(void) rtems_interrupt_handler_install(
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TEST_INTERRUPT_SOURCE,
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"tm27 low",
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RTEMS_INTERRUPT_SHARED,
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(rtems_interrupt_handler) handler,
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NULL
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);
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(void) rtems_interrupt_handler_install(
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TEST_INTERRUPT_SOURCE2,
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"tm27 high",
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RTEMS_INTERRUPT_SHARED,
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(rtems_interrupt_handler) handler,
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NULL
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);
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}
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#define Cause_tm27_intr() \
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do { \
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ERC32_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1) ); \
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nop(); \
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nop(); \
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nop(); \
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} while (0)
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#define Clear_tm27_intr() \
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ERC32_Clear_interrupt( TEST_INTERRUPT_SOURCE )
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#define Lower_tm27_intr() /* empty */
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#endif
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#endif
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