forked from Imagelibrary/rtems
a434cc80cb
Note: The changes have been done with portability in mind. The driver should (in theory) be able to replace the original one in the MPC BSPs too. For full compatibility an adaption layer and especially a test would be necessary. Because both are missing, don't integrate it into the MPC BSP now. Update #4180
376 lines
11 KiB
C
376 lines
11 KiB
C
/**
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* @file
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*
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* @ingroup RTEMSBSPsSharedFslEDMA
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*
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* @brief Freescale / NXP Enhanced Direct Memory Access (eDMA).
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*/
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/*
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* Copyright (C) 2008-2020 embedded brains GmbH (http://www.embedded-brains.de)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef LIBBSP_SHARED_FSL_EDMA_H
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#define LIBBSP_SHARED_FSL_EDMA_H
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#include <fsl/regs-edma.h>
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#include <rtems.h>
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#include <rtems/chain.h>
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#ifdef LIBBSP_ARM_IMXRT_BSP_H
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#define EDMA_CHANNEL_COUNT 32U
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#elif MPC55XX_CHIP_FAMILY == 551
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#define EDMA_CHANNEL_COUNT 16U
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#elif MPC55XX_CHIP_FAMILY == 564
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#define EDMA_CHANNEL_COUNT 16U
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#elif MPC55XX_CHIP_FAMILY == 567
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#define EDMA_CHANNEL_COUNT 96U
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#else
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#define EDMA_CHANNEL_COUNT 64U
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#endif
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#define EDMA_MODULE_COUNT ((EDMA_CHANNEL_COUNT + 63U) / 64U)
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#define EDMA_CHANNELS_PER_MODULE 64U
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volatile struct fsl_edma_tcd *fsl_edma_tcd_of_channel_index(unsigned index);
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unsigned fsl_edma_channel_index_of_tcd(volatile struct fsl_edma_tcd *edma_tcd);
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#ifdef LIBBSP_POWERPC_MPC55XXEVB_BSP_H
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#error Legacy stuff. Move to compatibility layer.
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#if EDMA_MODULE_COUNT == 1
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#define EDMA_TCD_BY_CHANNEL_INDEX(channel_index) \
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(&EDMA.TCD[(channel_index)])
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#elif EDMA_MODULE_COUNT == 2
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#define EDMA_TCD_BY_CHANNEL_INDEX(channel_index) \
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((channel_index) < EDMA_CHANNELS_PER_MODULE ? \
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&EDMA_A.TCD[(channel_index)] \
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: &EDMA_B.TCD[(channel_index) - EDMA_CHANNELS_PER_MODULE])
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#else
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#error "unsupported module count"
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#endif
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#endif
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#ifdef LIBBSP_POWERPC_MPC55XXEVB_BSP_H
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typedef enum {
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/* FIXME: These values are only valid for the MPC5566 and MPC5674F */
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EDMA_EQADC_A_FISR0_CFFF0 = 0,
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EDMA_EQADC_A_FISR0_RFDF0 = 1,
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EDMA_EQADC_A_FISR1_CFFF1 = 2,
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EDMA_EQADC_A_FISR1_RFDF1 = 3,
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EDMA_EQADC_A_FISR2_CFFF2 = 4,
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EDMA_EQADC_A_FISR2_RFDF2 = 5,
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EDMA_EQADC_A_FISR3_CFFF3 = 6,
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EDMA_EQADC_A_FISR3_RFDF3 = 7,
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EDMA_EQADC_A_FISR4_CFFF4 = 8,
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EDMA_EQADC_A_FISR4_RFDF4 = 9,
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EDMA_EQADC_A_FISR5_CFFF5 = 10,
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EDMA_EQADC_A_FISR5_RFDF5 = 11,
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EDMA_DSPI_B_SR_TFFF = 12,
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EDMA_DSPI_B_SR_RFDF = 13,
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EDMA_DSPI_C_SR_TFFF = 14,
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EDMA_DSPI_C_SR_RFDF = 15,
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EDMA_DSPI_D_SR_TFFF = 16,
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EDMA_DSPI_D_SR_RFDF = 17,
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EDMA_ESCI_A_COMBTX = 18,
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EDMA_ESCI_A_COMBRX = 19,
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EDMA_EMIOS_GFR_F0 = 20,
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EDMA_EMIOS_GFR_F1 = 21,
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EDMA_EMIOS_GFR_F2 = 22,
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EDMA_EMIOS_GFR_F3 = 23,
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EDMA_EMIOS_GFR_F4 = 24,
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EDMA_EMIOS_GFR_F8 = 25,
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EDMA_EMIOS_GFR_F9 = 26,
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EDMA_ETPU_CDTRSR_A_DTRS0 = 27,
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EDMA_ETPU_CDTRSR_A_DTRS1 = 28,
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EDMA_ETPU_CDTRSR_A_DTRS2 = 29,
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EDMA_ETPU_CDTRSR_A_DTRS14 = 30,
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EDMA_ETPU_CDTRSR_A_DTRS15 = 31,
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EDMA_DSPI_A_SR_TFFF = 32,
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EDMA_DSPI_A_SR_RFDF = 33,
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EDMA_ESCI_B_COMBTX = 34,
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EDMA_ESCI_B_COMBRX = 35,
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EDMA_EMIOS_GFR_F6 = 36,
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EDMA_EMIOS_GFR_F7 = 37,
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EDMA_EMIOS_GFR_F10 = 38,
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EDMA_EMIOS_GFR_F11 = 39,
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EDMA_EMIOS_GFR_F16 = 40,
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EDMA_EMIOS_GFR_F17 = 41,
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EDMA_EMIOS_GFR_F18 = 42,
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EDMA_EMIOS_GFR_F19 = 43,
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EDMA_ETPU_CDTRSR_A_DTRS12 = 44,
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EDMA_ETPU_CDTRSR_A_DTRS13 = 45,
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EDMA_ETPU_CDTRSR_A_DTRS28 = 46,
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EDMA_ETPU_CDTRSR_A_DTRS29 = 47,
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EDMA_SIU_EISR_EIF0 = 48,
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EDMA_SIU_EISR_EIF1 = 49,
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EDMA_SIU_EISR_EIF2 = 50,
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EDMA_SIU_EISR_EIF3 = 51,
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EDMA_ETPU_CDTRSR_B_DTRS0 = 52,
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EDMA_ETPU_CDTRSR_B_DTRS1 = 53,
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EDMA_ETPU_CDTRSR_B_DTRS2 = 54,
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EDMA_ETPU_CDTRSR_B_DTRS3 = 55,
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EDMA_ETPU_CDTRSR_B_DTRS12 = 56,
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EDMA_ETPU_CDTRSR_B_DTRS13 = 57,
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EDMA_ETPU_CDTRSR_B_DTRS14 = 58,
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EDMA_ETPU_CDTRSR_B_DTRS15 = 59,
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EDMA_ETPU_CDTRSR_B_DTRS28 = 60,
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EDMA_ETPU_CDTRSR_B_DTRS29 = 61,
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EDMA_ETPU_CDTRSR_B_DTRS30 = 62,
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EDMA_ETPU_CDTRSR_B_DTRS31 = 63
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#if MPC55XX_CHIP_FAMILY == 567
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,
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EDMA_EQADC_B_FISR0_CFFF0 = 64 + 0,
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EDMA_EQADC_B_FISR0_RFDF0 = 64 + 1,
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EDMA_EQADC_B_FISR1_CFFF1 = 64 + 2,
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EDMA_EQADC_B_FISR1_RFDF1 = 64 + 3,
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EDMA_EQADC_B_FISR2_CFFF2 = 64 + 4,
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EDMA_EQADC_B_FISR2_RFDF2 = 64 + 5,
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EDMA_EQADC_B_FISR3_CFFF3 = 64 + 6,
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EDMA_EQADC_B_FISR3_RFDF3 = 64 + 7,
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EDMA_EQADC_B_FISR4_CFFF4 = 64 + 8,
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EDMA_EQADC_B_FISR4_RFDF4 = 64 + 9,
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EDMA_EQADC_B_FISR5_CFFF5 = 64 + 10,
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EDMA_EQADC_B_FISR5_RFDF5 = 64 + 11,
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EDMA_DECFILTER_A_IB = 64 + 12,
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EDMA_DECFILTER_A_OB = 64 + 13,
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EDMA_DECFILTER_B_IB = 64 + 14,
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EDMA_DECFILTER_B_OB = 64 + 15,
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EDMA_DECFILTER_C_IB = 64 + 16,
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EDMA_DECFILTER_C_OB = 64 + 17,
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EDMA_DECFILTER_D_IB = 64 + 18,
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EDMA_DECFILTER_D_OB = 64 + 19,
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EDMA_DECFILTER_E_IB = 64 + 20,
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EDMA_DECFILTER_E_OB = 64 + 21,
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EDMA_DECFILTER_F_IB = 64 + 22,
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EDMA_DECFILTER_F_OB = 64 + 23,
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EDMA_DECFILTER_G_IB = 64 + 24,
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EDMA_DECFILTER_G_OB = 64 + 25,
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EDMA_DECFILTER_H_IB = 64 + 26,
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EDMA_DECFILTER_H_OB = 64 + 27
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#endif
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} fsl_edma_channel;
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#endif
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typedef struct fsl_edma_channel_context {
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rtems_chain_node node;
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volatile struct fsl_edma_tcd *edma_tcd;
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void (*done)(struct fsl_edma_channel_context *, uint32_t);
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} fsl_edma_channel_context;
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void fsl_edma_init(void);
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/**
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* @brief Obtains an eDMA channel.
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*
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* @retval RTEMS_SUCCESSFUL Successful operation.
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* @retval RTEMS_RESOURCE_IN_USE The channel is already in use.
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*/
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rtems_status_code fsl_edma_obtain_channel_by_tcd(
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volatile struct fsl_edma_tcd *edma_tcd
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);
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void fsl_edma_release_channel_by_tcd(volatile struct fsl_edma_tcd *edma_tcd);
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/**
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* @brief Obtains a specific eDMA channel and registers the channel context.
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*
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* Tries to obtain the channel specified in the @a ctx.
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*
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* @a irq_priority will be ignored on all targets but MPC55xx based ones.
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*
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* The done handler of the channel context will be called
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* - during minor or major loop completions if interrupts are enabled in the
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* corresponding TCD, or
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* - in case a channel error occurs.
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*
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* An error status value not equal to zero indicates an error.
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*
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* @retval RTEMS_SUCCESSFUL Successful operation.
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* @retval RTEMS_RESOURCE_IN_USE The channel is already in use.
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* @retval RTEMS_IO_ERROR Unable to install interrupt handler for this channel.
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*/
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rtems_status_code fsl_edma_obtain_channel(
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fsl_edma_channel_context *ctx,
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unsigned irq_priority
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);
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/**
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* @brief Obtains a free eDMA channel and registers the channel context.
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*
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* Tries to obtain the next free DMA channel. The tcd field of @a ctx will be
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* set accordingly.
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*
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* The done handler of the channel context will be called
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* - during minor or major loop completions if interrupts are enabled in the
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* corresponding TCD, or
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* - in case a channel error occurs.
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*
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* An error status value not equal to zero indicates an error.
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*
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* @retval RTEMS_SUCCESSFUL Successful operation.
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* @retval RTEMS_RESOURCE_IN_USE No channels left.
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* @retval RTEMS_IO_ERROR Unable to install interrupt handler.
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*/
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rtems_status_code fsl_edma_obtain_next_free_channel(
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fsl_edma_channel_context *ctx
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);
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void fsl_edma_release_channel(fsl_edma_channel_context *ctx);
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/**
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* @brief Copies a source TCD to an eDMA TCD.
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*
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* The DONE flag of the eDMA TCD is cleared before the actual copy operation.
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* This enables the setting of channel link or scatter/gather options.
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*
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* This function can be used to start the channel if the START flags is
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* set in the source TCD.
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*/
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void fsl_edma_copy(
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volatile struct fsl_edma_tcd *edma_tcd,
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const struct fsl_edma_tcd *source_tcd
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);
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/**
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* @brief Copies a source TCD to an eDMA TCD and enables hardware requests.
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*
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* The DONE flag of the eDMA TCD is cleared before the actual copy operation.
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* This enables the setting of channel link or scatter/gather options.
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*/
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void fsl_edma_copy_and_enable_hardware_requests(
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volatile struct fsl_edma_tcd *edma_tcd,
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const struct fsl_edma_tcd *source_tcd
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);
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void fsl_edma_sg_link(
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volatile struct fsl_edma_tcd *edma_tcd,
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const struct fsl_edma_tcd *source_tcd
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);
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static inline volatile struct fsl_edma *fsl_edma_by_tcd(
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volatile struct fsl_edma_tcd *edma_tcd
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)
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{
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return (volatile struct fsl_edma *)
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((uintptr_t) edma_tcd & ~(uintptr_t) 0x1fff);
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}
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static inline unsigned fsl_edma_channel_by_tcd(
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volatile struct fsl_edma_tcd *edma_tcd
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)
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{
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volatile struct fsl_edma *edma = fsl_edma_by_tcd(edma_tcd);
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return edma_tcd - &edma->TCD[0];
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}
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static inline void fsl_edma_enable_hardware_requests(
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volatile struct fsl_edma_tcd *edma_tcd
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)
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{
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volatile struct fsl_edma *edma = fsl_edma_by_tcd(edma_tcd);
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unsigned channel = edma_tcd - &edma->TCD[0];
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edma->SERQR = (uint8_t) channel;
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}
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static inline void fsl_edma_disable_hardware_requests(
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volatile struct fsl_edma_tcd *edma_tcd
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)
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{
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volatile struct fsl_edma *edma = fsl_edma_by_tcd(edma_tcd);
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unsigned channel = edma_tcd - &edma->TCD[0];
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edma->CERQR = (uint8_t) channel;
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}
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static inline void fsl_edma_enable_error_interrupts(
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volatile struct fsl_edma_tcd *edma_tcd
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)
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{
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volatile struct fsl_edma *edma = fsl_edma_by_tcd(edma_tcd);
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unsigned channel = edma_tcd - &edma->TCD[0];
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edma->SEEIR = (uint8_t) channel;
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}
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static inline void fsl_edma_disable_error_interrupts(
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volatile struct fsl_edma_tcd *edma_tcd
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)
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{
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volatile struct fsl_edma *edma = fsl_edma_by_tcd(edma_tcd);
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unsigned channel = edma_tcd - &edma->TCD[0];
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edma->CEEIR = (uint8_t) channel;
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}
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static inline void fsl_edma_set_start(
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volatile struct fsl_edma_tcd *edma_tcd
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)
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{
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volatile struct fsl_edma *edma = fsl_edma_by_tcd(edma_tcd);
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unsigned channel = edma_tcd - &edma->TCD[0];
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edma->SSBR = (uint8_t) channel;
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}
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static inline void fsl_edma_clear_done(
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volatile struct fsl_edma_tcd *edma_tcd
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)
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{
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volatile struct fsl_edma *edma = fsl_edma_by_tcd(edma_tcd);
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unsigned channel = edma_tcd - &edma->TCD[0];
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edma->CDSBR = (uint8_t) channel;
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}
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static inline void fsl_edma_clear_interrupts(
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volatile struct fsl_edma_tcd *edma_tcd
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)
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{
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volatile struct fsl_edma *edma = fsl_edma_by_tcd(edma_tcd);
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unsigned channel = edma_tcd - &edma->TCD[0];
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edma->CIRQR = (uint8_t) channel;
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}
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static inline bool fsl_edma_is_done(
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volatile struct fsl_edma_tcd *edma_tcd
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)
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{
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return ((edma_tcd->BMF & EDMA_TCD_BMF_DONE) != 0);
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}
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* LIBBSP_SHARED_FSL_EDMA_H */
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