forked from Imagelibrary/rtems
f0859573f9
This moves the zynq-uart driver from bsps/arm/shared to bsps/shared to accomodate use by AArch64 BSPs.
164 lines
6.9 KiB
C
164 lines
6.9 KiB
C
/**
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* @file
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* @ingroup zynq_uart_regs
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* @brief UART register definitions.
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*/
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (C) 2013 embedded brains GmbH
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @defgroup zynq_uart_regs UART Register Definitions
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* @ingroup zynq_uart
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* @brief UART Register Definitions
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* @{
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*/
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#ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H
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#define LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H
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#include <bsp/utility.h>
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#define ZYNQ_UART_FIFO_DEPTH 64
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typedef struct zynq_uart {
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uint32_t control;
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#define ZYNQ_UART_CONTROL_STPBRK BSP_BIT32(8)
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#define ZYNQ_UART_CONTROL_STTBRK BSP_BIT32(7)
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#define ZYNQ_UART_CONTROL_RSTTO BSP_BIT32(6)
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#define ZYNQ_UART_CONTROL_TXDIS BSP_BIT32(5)
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#define ZYNQ_UART_CONTROL_TXEN BSP_BIT32(4)
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#define ZYNQ_UART_CONTROL_RXDIS BSP_BIT32(3)
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#define ZYNQ_UART_CONTROL_RXEN BSP_BIT32(2)
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#define ZYNQ_UART_CONTROL_TXRES BSP_BIT32(1)
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#define ZYNQ_UART_CONTROL_RXRES BSP_BIT32(0)
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uint32_t mode;
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#define ZYNQ_UART_MODE_CHMODE(val) BSP_FLD32(val, 8, 9)
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#define ZYNQ_UART_MODE_CHMODE_GET(reg) BSP_FLD32GET(reg, 8, 9)
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#define ZYNQ_UART_MODE_CHMODE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9)
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#define ZYNQ_UART_MODE_CHMODE_NORMAL 0x00U
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#define ZYNQ_UART_MODE_CHMODE_AUTO_ECHO 0x01U
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#define ZYNQ_UART_MODE_CHMODE_LOCAL_LOOPBACK 0x02U
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#define ZYNQ_UART_MODE_CHMODE_REMOTE_LOOPBACK 0x03U
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#define ZYNQ_UART_MODE_NBSTOP(val) BSP_FLD32(val, 6, 7)
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#define ZYNQ_UART_MODE_NBSTOP_GET(reg) BSP_FLD32GET(reg, 6, 7)
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#define ZYNQ_UART_MODE_NBSTOP_SET(reg, val) BSP_FLD32SET(reg, val, 6, 7)
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#define ZYNQ_UART_MODE_NBSTOP_STOP_1 0x00U
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#define ZYNQ_UART_MODE_NBSTOP_STOP_1_5 0x01U
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#define ZYNQ_UART_MODE_NBSTOP_STOP_2 0x02U
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#define ZYNQ_UART_MODE_PAR(val) BSP_FLD32(val, 3, 5)
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#define ZYNQ_UART_MODE_PAR_GET(reg) BSP_FLD32GET(reg, 3, 5)
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#define ZYNQ_UART_MODE_PAR_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
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#define ZYNQ_UART_MODE_PAR_EVEN 0x00U
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#define ZYNQ_UART_MODE_PAR_ODD 0x01U
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#define ZYNQ_UART_MODE_PAR_SPACE 0x02U
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#define ZYNQ_UART_MODE_PAR_MARK 0x03U
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#define ZYNQ_UART_MODE_PAR_NONE 0x04U
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#define ZYNQ_UART_MODE_CHRL(val) BSP_FLD32(val, 1, 2)
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#define ZYNQ_UART_MODE_CHRL_GET(reg) BSP_FLD32GET(reg, 1, 2)
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#define ZYNQ_UART_MODE_CHRL_SET(reg, val) BSP_FLD32SET(reg, val, 1, 2)
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#define ZYNQ_UART_MODE_CHRL_8 0x00U
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#define ZYNQ_UART_MODE_CHRL_7 0x02U
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#define ZYNQ_UART_MODE_CHRL_6 0x03U
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#define ZYNQ_UART_MODE_CLKS BSP_BIT32(0)
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uint32_t irq_en;
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uint32_t irq_dis;
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uint32_t irq_mask;
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uint32_t irq_sts;
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#define ZYNQ_UART_TOVR BSP_BIT32(12)
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#define ZYNQ_UART_TNFUL BSP_BIT32(11)
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#define ZYNQ_UART_TTRIG BSP_BIT32(10)
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#define ZYNQ_UART_DMSI BSP_BIT32(9)
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#define ZYNQ_UART_TIMEOUT BSP_BIT32(8)
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#define ZYNQ_UART_PARE BSP_BIT32(7)
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#define ZYNQ_UART_FRAME BSP_BIT32(6)
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#define ZYNQ_UART_ROVR BSP_BIT32(5)
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#define ZYNQ_UART_TFUL BSP_BIT32(4)
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#define ZYNQ_UART_TEMPTY BSP_BIT32(3)
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#define ZYNQ_UART_RFUL BSP_BIT32(2)
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#define ZYNQ_UART_REMPTY BSP_BIT32(1)
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#define ZYNQ_UART_RTRIG BSP_BIT32(0)
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uint32_t baud_rate_gen;
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#define ZYNQ_UART_BAUD_RATE_GEN_CD(val) BSP_FLD32(val, 0, 15)
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#define ZYNQ_UART_BAUD_RATE_GEN_CD_GET(reg) BSP_FLD32GET(reg, 0, 15)
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#define ZYNQ_UART_BAUD_RATE_GEN_CD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
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uint32_t rx_timeout;
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#define ZYNQ_UART_RX_TIMEOUT_RTO(val) BSP_FLD32(val, 0, 7)
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#define ZYNQ_UART_RX_TIMEOUT_RTO_GET(reg) BSP_FLD32GET(reg, 0, 7)
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#define ZYNQ_UART_RX_TIMEOUT_RTO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
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uint32_t rx_fifo_trg_lvl;
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#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG(val) BSP_FLD32(val, 0, 5)
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#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5)
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#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
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uint32_t modem_ctrl;
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#define ZYNQ_UART_MODEM_CTRL_FCM BSP_BIT32(5)
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#define ZYNQ_UART_MODEM_CTRL_RTS BSP_BIT32(1)
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#define ZYNQ_UART_MODEM_CTRL_DTR BSP_BIT32(0)
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uint32_t modem_sts;
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#define ZYNQ_UART_MODEM_STS_FCMS BSP_BIT32(8)
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#define ZYNQ_UART_MODEM_STS_DCD BSP_BIT32(7)
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#define ZYNQ_UART_MODEM_STS_RI BSP_BIT32(6)
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#define ZYNQ_UART_MODEM_STS_DSR BSP_BIT32(5)
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#define ZYNQ_UART_MODEM_STS_CTS BSP_BIT32(4)
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#define ZYNQ_UART_MODEM_STS_DDCD BSP_BIT32(3)
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#define ZYNQ_UART_MODEM_STS_TERI BSP_BIT32(2)
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#define ZYNQ_UART_MODEM_STS_DDSR BSP_BIT32(1)
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#define ZYNQ_UART_MODEM_STS_DCTS BSP_BIT32(0)
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uint32_t channel_sts;
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#define ZYNQ_UART_CHANNEL_STS_TNFUL BSP_BIT32(14)
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#define ZYNQ_UART_CHANNEL_STS_TTRIG BSP_BIT32(13)
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#define ZYNQ_UART_CHANNEL_STS_FDELT BSP_BIT32(12)
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#define ZYNQ_UART_CHANNEL_STS_TACTIVE BSP_BIT32(11)
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#define ZYNQ_UART_CHANNEL_STS_RACTIVE BSP_BIT32(10)
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#define ZYNQ_UART_CHANNEL_STS_TFUL BSP_BIT32(4)
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#define ZYNQ_UART_CHANNEL_STS_TEMPTY BSP_BIT32(3)
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#define ZYNQ_UART_CHANNEL_STS_RFUL BSP_BIT32(2)
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#define ZYNQ_UART_CHANNEL_STS_REMPTY BSP_BIT32(1)
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#define ZYNQ_UART_CHANNEL_STS_RTRIG BSP_BIT32(0)
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uint32_t tx_rx_fifo;
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#define ZYNQ_UART_TX_RX_FIFO_FIFO(val) BSP_FLD32(val, 0, 7)
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#define ZYNQ_UART_TX_RX_FIFO_FIFO_GET(reg) BSP_FLD32GET(reg, 0, 7)
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#define ZYNQ_UART_TX_RX_FIFO_FIFO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
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uint32_t baud_rate_div;
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#define ZYNQ_UART_BAUD_RATE_DIV_BDIV(val) BSP_FLD32(val, 0, 7)
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#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_GET(reg) BSP_FLD32GET(reg, 0, 7)
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#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
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uint32_t flow_delay;
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#define ZYNQ_UART_FLOW_DELAY_FDEL(val) BSP_FLD32(val, 0, 5)
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#define ZYNQ_UART_FLOW_DELAY_FDEL_GET(reg) BSP_FLD32GET(reg, 0, 5)
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#define ZYNQ_UART_FLOW_DELAY_FDEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
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uint32_t reserved_3c[2];
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uint32_t tx_fifo_trg_lvl;
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#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG(val) BSP_FLD32(val, 0, 5)
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#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5)
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#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
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} zynq_uart;
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/** @} */
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#endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H */
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