forked from Imagelibrary/rtems
70 lines
2.2 KiB
ArmAsm
70 lines
2.2 KiB
ArmAsm
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (C) 2018 embedded brains GmbH
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <rtems/asm.h>
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#include <dev/cache/arm-data-cache-loop-set-way.h>
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#if __ARM_ARCH >= 7 && (__ARM_ARCH_PROFILE == 'A' || __ARM_ARCH_PROFILE == 'R')
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.globl rtems_cache_disable_data
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.syntax unified
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.section .text
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.arm
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/*
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* This function disables the data cache on an ARMv7-AR compatible
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* processor.
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*/
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FUNCTION_ENTRY(rtems_cache_disable_data)
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/* Disable interrupts */
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mrs r0, CPSR
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orr r1, r0, #0x80
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msr CPSR_fc, r1
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stmdb sp!, {r4 - r11, lr}
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dmb
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/* Disable data cache in SCTLR */
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mrc p15, 0, r1, c1, c0, 0
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bic r1, r1, #0x4
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mcr p15, 0, r1, c1, c0, 0
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isb
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/*
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* Clean and invalidate the sets and ways of all data or unified cache
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* levels using DCCISW (Data Cache line Clean and Invalidate by
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* Set/Way).
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*/
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ARM_DATA_CACHE_LOOP_SET_WAY c14
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/* Restore interrupts */
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msr CPSR_fc, r0
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ldmia sp!, {r4 - r11, pc}
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#endif
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