forked from Imagelibrary/rtems
257 lines
6.8 KiB
C
257 lines
6.8 KiB
C
/*
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* AMD 29K CPU Dependent Source
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*
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* Author: Craig Lebakken <craigl@transition.com>
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*
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* COPYRIGHT (c) 1996 by Transition Networks Inc.
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*
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* To anyone who acknowledges that this file is provided "AS IS"
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* without any express or implied warranty:
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* permission to use, copy, modify, and distribute this file
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* for any purpose is hereby granted without fee, provided that
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* the above copyright notice and this notice appears in all
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* copies, and that the name of Transition Networks not be used in
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* advertising or publicity pertaining to distribution of the
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* software without specific, written prior permission.
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* Transition Networks makes no representations about the suitability
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* of this software for any purpose.
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*
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* Derived from c/src/exec/score/cpu/no_cpu/cpu.c:
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*
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* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
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* On-Line Applications Research Corporation (OAR).
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* All rights assigned to U.S. Government, 1994.
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*
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* This material may be reproduced by or for the U.S. Government pursuant
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* to the copyright license under the clause at DFARS 252.227-7013. This
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* notice must appear in all copies of this file and its derivatives.
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*
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* $Id$
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*/
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#ifndef lint
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static char _sccsid[] = "@(#)cpu.c 21 Aug 1996 1.6\n";
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#endif
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#include <rtems/system.h>
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#include <rtems/score/isr.h>
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#include <rtems/score/wkspace.h>
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#include <rtems/score/thread.h>
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#include <stdio.h>
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#include <stdlib.h>
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void a29k_ISR_Handler(unsigned32 vector);
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/* _CPU_Initialize
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*
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* This routine performs processor dependent initialization.
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*
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* INPUT PARAMETERS:
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* cpu_table - CPU table to initialize
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* thread_dispatch - address of disptaching routine
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*/
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void _CPU_Initialize(
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rtems_cpu_table *cpu_table,
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void (*thread_dispatch)() /* ignored on this CPU */
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)
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{
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unsigned int i;
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/*
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* The thread_dispatch argument is the address of the entry point
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* for the routine called at the end of an ISR once it has been
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* decided a context switch is necessary. On some compilation
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* systems it is difficult to call a high-level language routine
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* from assembly. This allows us to trick these systems.
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*
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* If you encounter this problem save the entry point in a CPU
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* dependent variable.
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*/
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_CPU_Thread_dispatch_pointer = thread_dispatch;
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/*
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* If there is not an easy way to initialize the FP context
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* during Context_Initialize, then it is usually easier to
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* save an "uninitialized" FP context here and copy it to
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* the task's during Context_Initialize.
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*/
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/* FP context initialization support goes here */
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_CPU_Table = *cpu_table;
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for ( i = 0; i < ISR_NUMBER_OF_VECTORS; i++ )
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{
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_ISR_Vector_table[i] = (proc_ptr)NULL;
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}
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}
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/*PAGE
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*
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* _CPU_ISR_Get_level
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*/
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unsigned32 _CPU_ISR_Get_level( void )
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{
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/*
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* This routine returns the current interrupt level.
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*/
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return 0;
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}
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/*PAGE
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*
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* _CPU_ISR_install_raw_handler
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*/
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extern void intr14( void );
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extern void intr3( void );
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extern void intr2( void );
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void _CPU_ISR_install_raw_handler(
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unsigned32 vector,
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proc_ptr new_handler,
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proc_ptr *old_handler
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)
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{
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/*
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* This is where we install the interrupt handler into the "raw" interrupt
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* table used by the CPU to dispatch interrupt handlers.
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*/
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switch( vector )
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{
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case 14:
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_settrap( vector, intr14 );
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break;
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case 3:
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_settrap( vector, intr3 );
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break;
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case 2:
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_settrap( vector, intr2 );
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break;
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default:
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break;
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}
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}
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/*PAGE
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*
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* _CPU_ISR_install_vector
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*
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* This kernel routine installs the RTEMS handler for the
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* specified vector.
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*
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* Input parameters:
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* vector - interrupt vector number
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* old_handler - former ISR for this vector number
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* new_handler - replacement ISR for this vector number
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*
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* Output parameters: NONE
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*
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*/
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void _CPU_ISR_install_vector(
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unsigned32 vector,
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proc_ptr new_handler,
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proc_ptr *old_handler
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)
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{
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*old_handler = _ISR_Vector_table[ vector ];
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/*
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* If the interrupt vector table is a table of pointer to isr entry
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* points, then we need to install the appropriate RTEMS interrupt
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* handler for this vector number.
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*/
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_CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
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/*
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* We put the actual user ISR address in '_ISR_vector_table'. This will
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* be used by the _ISR_Handler so the user gets control.
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*/
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_ISR_Vector_table[ vector ] = new_handler;
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}
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/*PAGE
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*
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* _CPU_Install_interrupt_stack
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*/
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void _CPU_Install_interrupt_stack( void )
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{
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}
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/*PAGE
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*
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* _CPU_Internal_threads_Idle_thread_body
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*
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* NOTES:
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*
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* 1. This is the same as the regular CPU independent algorithm.
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*
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* 2. If you implement this using a "halt", "idle", or "shutdown"
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* instruction, then don't forget to put it in an infinite loop.
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*
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* 3. Be warned. Some processors with onboard DMA have been known
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* to stop the DMA if the CPU were put in IDLE mode. This might
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* also be a problem with other on-chip peripherals. So use this
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* hook with caution.
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*/
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void _CPU_Internal_threads_Idle_thread_body( void )
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{
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for( ; ; )
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{
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}
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/* insert your "halt" instruction here */ ;
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}
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void a29k_fatal_error( unsigned32 error )
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{
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printf("\n\nfatal error %d, rebooting!!!\n",error );
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exit(error);
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}
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/*
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* This discussion ignores a lot of the ugly details in a real
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* implementation such as saving enough registers/state to be
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* able to do something real. Keep in mind that the goal is
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* to invoke a user's ISR handler which is written in C and
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* uses a certain set of registers.
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*
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* Also note that the exact order is to a large extent flexible.
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* Hardware will dictate a sequence for a certain subset of
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* _ISR_Handler while requirements for setting
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*/
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/*
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* At entry to "common" _ISR_Handler, the vector number must be
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* available. On some CPUs the hardware puts either the vector
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* number or the offset into the vector table for this ISR in a
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* known place. If the hardware does not give us this information,
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* then the assembly portion of RTEMS for this port will contain
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* a set of distinct interrupt entry points which somehow place
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* the vector number in a known place (which is safe if another
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* interrupt nests this one) and branches to _ISR_Handler.
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*
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*/
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void a29k_ISR_Handler(unsigned32 vector)
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{
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_ISR_Nest_level++;
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_Thread_Dispatch_disable_level++;
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if ( _ISR_Vector_table[ vector ] )
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(*_ISR_Vector_table[ vector ])( vector );
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--_Thread_Dispatch_disable_level;
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--_ISR_Nest_level;
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if ( !_Thread_Dispatch_disable_level && !_ISR_Nest_level &&
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(_Context_Switch_necessary || _ISR_Signals_to_thread_executing ))
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_Thread_Dispatch();
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return;
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}
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