forked from Imagelibrary/rtems
1c189e1aa7
Add ref-clock-num identifiers to the device tree to ensure that interfaces use the correct clocks even when some are not used due to unconnected MII busses. This also adjusts the default ZynqMP PHY attachment to RGMII-ID which was the default before device trees were introduced.
99 lines
2.8 KiB
Plaintext
99 lines
2.8 KiB
Plaintext
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSBSPsAArch64XilinxZynqMP
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*
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* @brief This file provides the base ZynqMP device tree
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*/
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/*
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* Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
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* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/dts-v1/;
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/ {
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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amba {
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compatible = "simple-bus";
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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ranges;
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interrupt-controller@f9010000 {
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compatible = "arm,gic-400";
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#address-cells = <0x02>;
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#interrupt-cells = <0x03>;
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reg = <0x00 0xf9010000 0x00 0x10000>;
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interrupt-controller;
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phandle = <0x01>;
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};
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ethernet@ff0b0000 {
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compatible = "cdns,gem";
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status = "okay";
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x39 0x04>;
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reg = <0x00 0xff0b0000 0x00 0x1000>;
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phy-mode = "rgmii-id";
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ref-clock-num = <0>;
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};
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ethernet@ff0c0000 {
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compatible = "cdns,gem";
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status = "okay";
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x3b 0x04>;
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reg = <0x00 0xff0c0000 0x00 0x1000>;
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phy-mode = "rgmii-id";
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ref-clock-num = <1>;
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};
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ethernet@ff0d0000 {
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compatible = "cdns,gem";
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status = "okay";
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x3d 0x04>;
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reg = <0x00 0xff0d0000 0x00 0x1000>;
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phy-mode = "rgmii-id";
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ref-clock-num = <2>;
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};
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ethernet@ff0e0000 {
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compatible = "cdns,gem";
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status = "okay";
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x3f 0x04>;
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reg = <0x00 0xff0e0000 0x00 0x1000>;
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phy-mode = "rgmii-id";
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ref-clock-num = <3>;
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};
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};
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};
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