forked from Imagelibrary/rtems
371 lines
9.1 KiB
C
371 lines
9.1 KiB
C
/*
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* RTEMS generic MPC83xx BSP
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*
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* This file contains board specific definitions.
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*/
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/*
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* Copyright (c) 2007 embedded brains GmbH. All rights reserved.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef __GEN83xx_HWREG_VALS_h
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#define __GEN83xx_HWREG_VALS_h
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#include <mpc83xx/mpc83xx.h>
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#include <bsp.h>
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#ifdef MPC83XX_HAS_NAND_LP_FLASH_ON_CS0
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#define MPC83XX_RCWHR_BOOT_DEVICE (RCWHR_ROMLOC_LB08 | RCWHR_RLEXT_NAND)
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#else
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#define MPC83XX_RCWHR_BOOT_DEVICE (RCWHR_ROMLOC_LB16 | RCWHR_RLEXT_LGCY)
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#endif
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/*
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* distinguish board characteristics
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*/
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#if defined(MPC83XX_BOARD_MPC8349EAMDS)
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/*
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* for Freescale MPC8349 EAMDS
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*/
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/*
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* two DUART channels supported
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*/
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#define GEN83xx_DUART_AVAIL_MASK 0x03
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/* we need the low level initialization in start.S*/
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#define NEED_LOW_LEVEL_INIT
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/*
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* clocking infos
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*/
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#define BSP_CLKIN_FRQ 66000000L
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#define RCFG_SYSPLL_MF 4
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#define RCFG_COREPLL_MF 4
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/*
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* Reset configuration words
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*/
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#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \
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RCWLR_DDRCM_1_1 | \
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RCWLR_SPMF(RCFG_SYSPLL_MF) | \
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RCWLR_COREPLL(RCFG_COREPLL_MF))
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#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \
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RCWHR_PCI_32 | \
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RCWHR_PCI1ARB_EN | \
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RCWHR_PCI2ARB_EN | \
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RCWHR_CORE_EN | \
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RCWHR_BMS_LOW | \
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RCWHR_BOOTSEQ_NONE | \
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RCWHR_SW_DIS | \
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MPC83XX_RCWHR_BOOT_DEVICE | \
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RCWHR_TSEC1M_GMII | \
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RCWHR_TSEC2M_GMII | \
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RCWHR_ENDIAN_BIG | \
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RCWHR_LALE_NORM | \
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RCWHR_LDP_PAR)
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#elif defined(MPC83XX_BOARD_HSC_CM01)
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/*
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* for JPK HSC_CM01
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*/
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/*
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* one DUART channel (UART1) supported
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*/
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#define GEN83xx_DUART_AVAIL_MASK 0x01
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/* we need the low level initialization in start.S*/
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#define NEED_LOW_LEVEL_INIT
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/*
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* clocking infos
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*/
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#define BSP_CLKIN_FRQ 30000000L
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#define RCFG_SYSPLL_MF 11
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#define RCFG_COREPLL_MF 4
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/*
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* Reset configuration words
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*/
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#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \
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RCWLR_DDRCM_1_1 | \
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RCWLR_SPMF(RCFG_SYSPLL_MF) | \
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RCWLR_COREPLL(RCFG_COREPLL_MF))
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#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \
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RCWHR_PCI_32 | \
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RCWHR_PCI1ARB_DIS | \
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RCWHR_PCI2ARB_DIS | \
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RCWHR_CORE_EN | \
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RCWHR_BMS_LOW | \
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RCWHR_BOOTSEQ_NONE | \
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RCWHR_SW_DIS | \
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MPC83XX_RCWHR_BOOT_DEVICE | \
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RCWHR_TSEC1M_RGMII | \
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RCWHR_TSEC2M_GMII | \
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RCWHR_ENDIAN_BIG | \
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RCWHR_LALE_EARLY | \
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RCWHR_LDP_SPC)
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#elif defined(MPC83XX_BOARD_BR_UID)
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/*
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* for BR UID
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*/
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/*
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* one DUART channel (UART1) supported
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*/
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#define GEN83xx_DUART_AVAIL_MASK 0x01
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/* we need the low level initialization in start.S*/
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#define NEED_LOW_LEVEL_INIT
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/*
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* clocking infos
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*/
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#define BSP_CLKIN_FRQ 25000000L
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#define RCFG_SYSPLL_MF 5
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#define RCFG_COREPLL_MF 5
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/*
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* Reset configuration words
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*/
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#define RESET_CONF_WRD_L \
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(RCWLR_LBIUCM_1_1 \
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| RCWLR_DDRCM_2_1 \
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| RCWLR_SPMF(RCFG_SYSPLL_MF) \
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| RCWLR_COREPLL(RCFG_COREPLL_MF) \
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| RCWLR_CEVCOD_1_2 \
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| RCWLR_CEPMF(8) \
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)
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#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \
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RCWHR_PCI_32 | \
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RCWHR_PCI1ARB_DIS | \
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RCWHR_CORE_EN | \
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RCWHR_BMS_LOW | \
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RCWHR_BOOTSEQ_NONE | \
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RCWHR_SW_DIS | \
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MPC83XX_RCWHR_BOOT_DEVICE | \
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RCWHR_ENDIAN_BIG)
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#elif defined( HAS_UBOOT)
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/* TODO */
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#else
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#error "board type not defined"
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#endif
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#if defined(MPC83XX_BOARD_MPC8349EAMDS)
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/**************************
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* for Freescale MPC83XX_BOARD_MPC8349EAMDS
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*/
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/*
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* working values for various registers, used in start/start.S
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*/
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/*
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* Local Access Windows
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* FIXME: decode bit settings
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*/
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#define LBLAWBAR0_VAL 0xFE000000
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#define LBLAWAR0_VAL 0x80000016
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#define LBLAWBAR1_VAL 0xF8000000
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#define LBLAWAR1_VAL 0x8000000E
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#define LBLAWBAR2_VAL 0xF0000000
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#define LBLAWAR2_VAL 0x80000019
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#define DDRLAWBAR0_VAL 0x00000000
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#define DDRLAWAR0_VAL 0x8000001B
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/*
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* Local Bus (Memory) Controller
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* FIXME: decode bit settings
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*/
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#define BR0_VAL 0xFE001001
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#define OR0_VAL 0xFF806FF7
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#define BR1_VAL 0xF8000801
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#define OR1_VAL 0xFFFFE8F0
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#define BR2_VAL 0xF0001861
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#define OR2_VAL 0xFC006901
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/*
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* SDRAM registers
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* FIXME: decode bit settings
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*/
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#define MRPTR_VAL 0x20000000
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#define LSRT_VAL 0x32000000
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#define LSDMR_VAL 0x4062D733
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#define LCRR_VAL 0x80000004
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/*
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* DDR-SDRAM registers
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* FIXME: decode bit settings
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*/
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#define CS2_BNDS_VAL 0x00000007
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#define CS3_BNDS_VAL 0x0008000F
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#define CS2_CONFIG_VAL 0x80000101
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#define CS3_CONFIG_VAL 0x80000101
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#define TIMING_CFG_1_VAL 0x36333321
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#define TIMING_CFG_2_VAL 0x00000800
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#define DDR_SDRAM_CFG_VAL 0xC2000000
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#define DDR_SDRAM_MODE_VAL 0x00000022
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#define DDR_SDRAM_INTTVL_VAL 0x045B0100
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#define DDR_SDRAM_CLK_CNTL_VAL 0x00000000
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#elif defined(MPC83XX_BOARD_HSC_CM01)
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/**************************
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* for JPK HSC_CM01
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*/
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/*
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* working values for various registers, used in start/start.S
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*/
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/* fpga config 16 MB size */
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#define FPGA_CONFIG_START 0xF8000000
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#define FPGA_CONFIG_SIZE 0x01000000
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/* fpga register 8 MB size */
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#define FPGA_REGISTER_START 0xF9000000
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#define FPGA_REGISTER_SIZE 0x00800000
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/* fpga fifo 8 MB size */
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#define FPGA_FIFO_START 0xF9800000
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#define FPGA_FIFO_SIZE 0x00800000
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#define FPGA_START (FPGA_CONFIG_START)
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// fpga window size 32 MByte
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#define FPGA_SIZE (0x02000000)
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#define FPGA_END (FPGA_START+FPGA_SIZE-1)
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/*
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* Local Access Windows
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* FIXME: decode bit settings
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*/
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#define LBLAWBAR0_VAL bsp_rom_start
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#define LBLAWAR0_VAL 0x80000018
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#define LBLAWBAR1_VAL (FPGA_CONFIG_START)
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#define LBLAWAR1_VAL 0x80000018
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#define DDRLAWBAR0_VAL bsp_ram_start
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#define DDRLAWAR0_VAL 0x8000001B
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/*
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* Local Bus (Memory) Controller
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* FIXME: decode bit settings
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*/
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#define BR0_VAL (0xFE000000 | 0x01001)
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#define OR0_VAL 0xFE000E54
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// fpga config access range (UPM_A) (32 kByte)
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#define BR2_VAL (FPGA_CONFIG_START | 0x01881)
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#define OR2_VAL 0xFFFF9100
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// fpga register access range (UPM_B) (8 MByte)
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#define BR3_VAL (FPGA_REGISTER_START | 0x018A1)
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#define OR3_VAL 0xFF801100
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// fpga fifo access range (UPM_C) (8 MByte)
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#define BR4_VAL (FPGA_FIFO_START | 0x018C1)
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#define OR4_VAL 0xFF801100
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/*
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* SDRAM registers
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*/
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#define MRPTR_VAL 0x20000000
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#define LSRT_VAL 0x32000000
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#define LSDMR_VAL 0x4062D733
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#define LCRR_VAL 0x80010004
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/*
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* DDR-SDRAM registers
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* FIXME: decode bit settings
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*/
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#define DDRCDR_VAL 0x00000001
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#define CS0_BNDS_VAL 0x0000000F
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#define CS0_CONFIG_VAL 0x80810102
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#define TIMING_CFG_0_VAL 0x00420802
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#define TIMING_CFG_1_VAL 0x3735A322
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#define TIMING_CFG_2_VAL 0x2F9044C7
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#define DDR_SDRAM_CFG_2_VAL 0x00401000
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#define DDR_SDRAM_MODE_VAL 0x44521632
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#define DDR_SDRAM_CLK_CNTL_VAL 0x01800000
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#define DDR_SDRAM_CFG_VAL 0x63000008
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#define DDR_ERR_DISABLE_VAL 0x0000008D
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#define DDR_ERR_DISABLE_VAL2 0x00000089
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#define DDR_SDRAM_DATA_INIT_VAL 0xC01DCAFE
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#define DDR_SDRAM_INIT_ADDR_VAL 0
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#define DDR_SDRAM_INTERVAL_VAL 0x05080000
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#elif defined(MPC83XX_BOARD_BR_UID)
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/**************************
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* for BR UID
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*/
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/*
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* working values for various registers, used in start/start.S
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*/
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/*
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* Local Access Windows
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* FIXME: decode bit settings
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*/
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#define LBLAWBAR0_VAL bsp_rom_start
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#define LBLAWAR0_VAL 0x80000018
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#define DDRLAWBAR0_VAL bsp_ram_start
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#define DDRLAWAR0_VAL 0x8000001B
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/*
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* clocking for local bus:
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* ALE active for 1 clock
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* local bus clock = 1/2 csb clock
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*/
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#define LCRR_VAL 0x80010002
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/*
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* DDR-SDRAM registers
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* FIXME: decode bit settings
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*/
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#define DDRCDR_VAL 0x00000001
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#define CS0_BNDS_VAL 0x0000000F
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#define CS0_CONFIG_VAL 0x80014202
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#define TIMING_CFG_0_VAL 0x00220802
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#define TIMING_CFG_1_VAL 0x26259222
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#define TIMING_CFG_2_VAL 0x111048C7
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#define DDR_SDRAM_CFG_2_VAL 0x00401000
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#define DDR_SDRAM_MODE_VAL 0x200F1632
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#define DDR_SDRAM_MODE_2_VAL 0x40006000
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#define DDR_SDRAM_CLK_CNTL_VAL 0x01800000
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#define DDR_SDRAM_CFG_VAL 0x43100008
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#define DDR_ERR_DISABLE_VAL 0x0000008D
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#define DDR_ERR_DISABLE_VAL2 0x00000089
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#define DDR_SDRAM_DATA_INIT_VAL 0xC01DCAFE
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#define DDR_SDRAM_INIT_ADDR_VAL 0
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#define DDR_SDRAM_INTERVAL_VAL 0x01E8222E
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#elif defined( HAS_UBOOT)
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/* TODO */
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#else
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#error "board type not defined"
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#endif
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/**************************
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* derived values for all boards
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*/
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/* value of input clock divider (derived from pll mode reg) */
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#if MPC83XX_CHIP_TYPE != 8309
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#define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1)
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#else
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/* On the MPC8309 this bit is reserved */
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#define BSP_SYSPLL_CKID 1
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#endif
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/* value of system pll (derived from pll mode reg) */
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#define BSP_SYSPLL_MF ((mpc83xx.clk.spmr>>(31-7))&0x0f)
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/* value of system pll (derived from pll mode reg) */
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#define BSP_COREPLL_MF ((mpc83xx.clk.spmr>>(31-15))&0x7f)
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#endif /* __GEN83xx_HWREG_VALS_h */
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