forked from Imagelibrary/rtems
bc7313134f
The APIC timer is calibrated by running the i8254 PIT for a fraction of a second (determined by PIT_CALIBRATE_DIVIDER) and counting how many times the APIC counter has ticked. The calibration can be run multiple times (determined by APIC_TIMER_NUM_CALIBRATIONS) and averaged out. Updates #2898.
100 lines
3.6 KiB
C
100 lines
3.6 KiB
C
/*
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* Copyright (c) 2018.
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* Amaan Cheval <amaan.cheval@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _AMD64_CLOCK_H
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#define _AMD64_CLOCK_H
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#include <rtems/score/basedefs.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef ASM
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extern volatile uint32_t *amd64_apic_base;
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bool has_apic_support(void);
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void apic_initialize(void);
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void apic_timer_install_handler(void);
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uint32_t apic_timer_calibrate(void);
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void apic_timer_initialize(uint64_t desired_freq_hz);
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void amd64_clock_driver_initialize(void);
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#endif
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/* Number of times to calibrate the APIC timer to average it out */
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#define APIC_TIMER_NUM_CALIBRATIONS 5
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/* Default divide value used by APIC timer */
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#define APIC_TIMER_DIVIDE_VALUE 16
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/* Value to set in register to pick the divide value above */
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#define APIC_TIMER_SELECT_DIVIDER 3
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#define PIT_FREQUENCY 1193180
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/*
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* The PIT_FREQUENCY determines how many times the PIT counter is decremented
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* per second - therefore, we can calculate how many ticks we set based on what
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* fraction of a second we're okay with spending on calibration
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*/
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#define PIT_CALIBRATE_DIVIDER 20
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#define PIT_CALIBRATE_TICKS (PIT_FREQUENCY/PIT_CALIBRATE_DIVIDER)
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/* Since the PIT only has 2 one-byte registers, the maximum tick value is
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* limited to 16-bits. We can set the PIT to use a frequency divider if
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* needed. */
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RTEMS_STATIC_ASSERT(
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PIT_CALIBRATE_TICKS <= 0xffff,
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PIT_CALIBRATE_DIVIDER
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);
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/* I/O ports for the PIT */
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#define PIT_PORT_CHAN0 0x40
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#define PIT_PORT_CHAN1 0x41
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#define PIT_PORT_CHAN2 0x42
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/*
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* The input to channel 2 can be gated through software, using bit 0 of port
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* 0x61.
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*/
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#define PIT_PORT_CHAN2_GATE 0x61
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#define PIT_CHAN2_TIMER_BIT 1
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#define PIT_CHAN2_SPEAKER_BIT 2
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/* The PIT mode/command register */
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#define PIT_PORT_MCR 0x43
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/* PIT values to select channels, access, and operating modes */
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#define PIT_SELECT_CHAN0 0b00000000
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#define PIT_SELECT_CHAN1 0b01000000
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#define PIT_SELECT_CHAN2 0b10000000
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/*
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* In the lo/hi mode, the low-byte is sent to the data port, followed by the
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* high-byte; this makes it important that this be an atomic operation.
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*/
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#define PIT_SELECT_ACCESS_LOHI 0b00110000
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#define PIT_SELECT_ONE_SHOT_MODE 0b00000010
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#define PIT_SELECT_BINARY_MODE 0
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#ifdef __cplusplus
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}
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#endif
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#endif /* _AMD64_CLOCK_H */
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