forked from Imagelibrary/rtems
9964895866
Adjust build support files to new directory layout. This patch is a part of the BSP source reorganization. Update #3285.
50 lines
1.1 KiB
C
50 lines
1.1 KiB
C
/*
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* cpuinit.c - this file contains functions for initializing the CPU
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*
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* Written by Jay Monkman (jmonkman@frasca.com)
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*/
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#include <bsp.h>
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/* Macros for handling all the MMU SPRs */
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#define PUT_IC_CST(r) __asm__ volatile ("mtspr 0x230,%0\n" ::"r"(r))
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#define GET_IC_CST(r) __asm__ volatile ("mfspr %0,0x230\n" :"=r"(r))
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#define PUT_DC_CST(r) __asm__ volatile ("mtspr 0x238,%0\n" ::"r"(r))
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#define GET_DC_CST(r) __asm__ volatile ("mfspr %0,0x238\n" :"=r"(r))
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void cpu_init(void)
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{
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/* BRGCLK is VCO_OUT/4 */
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/*
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m8260.sccr = 0;
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*/
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#if 0
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register unsigned long t1, t2;
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/* Let's clear MSR[IR] and MSR[DR] */
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t2 = PPC_MSR_IR | PPC_MSR_DR;
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__asm__ volatile (
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"mfmsr %0\n"
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"andc %0, %0, %1\n"
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"mtmsr %0\n" :"=r"(t1), "=r"(t2):
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"1"(t2));
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t1 = M8xx_CACHE_CMD_UNLOCK;
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/* PUT_DC_CST(t1); */
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PUT_IC_CST(t1);
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t1 = M8xx_CACHE_CMD_INVALIDATE;
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/* PUT_DC_CST(t1); */
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PUT_IC_CST(t1);
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t1 = M8xx_CACHE_CMD_ENABLE;
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PUT_IC_CST(t1);
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t1 = M8xx_CACHE_CMD_SFWT;
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/* PUT_DC_CST(t1); */
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t1 = M8xx_CACHE_CMD_ENABLE;
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/* PUT_DC_CST(t1);*/
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#endif
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}
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