forked from Imagelibrary/rtems
127980c799
This patch updates the CPU_Exception_frame to include all necessary registers, combines hardware snd software exception handlers into a shared vector, provides an architecture-specific hook for taking control of exception handling, and moves exception handling over to actually using the CPU_Exception_frame instead of a minimal interrupt stack frame. As the significant contents of _exception_handler.S have been entirely rewritten, the copyright information on this file has been updated to reflect that.
104 lines
3.7 KiB
ArmAsm
104 lines
3.7 KiB
ArmAsm
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSBSPsMicroBlaze
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*
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* @brief MicroBlaze exception handler implementation
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*/
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/*
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* Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <rtems/score/cpu.h>
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.text
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.globl _exception_handler # Exception Handler Label
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.align 2
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_exception_handler:
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/* Subtract exception frame */
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addik r1, r1, -(CPU_EXCEPTION_FRAME_SIZE)
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/* Store program state */
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swi r2, r1, MICROBLAZE_EXCEPTION_FRAME_R2
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swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_R3
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swi r4, r1, MICROBLAZE_EXCEPTION_FRAME_R4
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swi r5, r1, MICROBLAZE_EXCEPTION_FRAME_R5
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swi r6, r1, MICROBLAZE_EXCEPTION_FRAME_R6
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swi r7, r1, MICROBLAZE_EXCEPTION_FRAME_R7
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swi r8, r1, MICROBLAZE_EXCEPTION_FRAME_R8
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swi r9, r1, MICROBLAZE_EXCEPTION_FRAME_R9
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swi r10, r1, MICROBLAZE_EXCEPTION_FRAME_R10
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swi r11, r1, MICROBLAZE_EXCEPTION_FRAME_R11
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swi r12, r1, MICROBLAZE_EXCEPTION_FRAME_R12
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swi r13, r1, MICROBLAZE_EXCEPTION_FRAME_R13
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swi r14, r1, MICROBLAZE_EXCEPTION_FRAME_R14
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swi r15, r1, MICROBLAZE_EXCEPTION_FRAME_R15
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swi r16, r1, MICROBLAZE_EXCEPTION_FRAME_R16
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swi r17, r1, MICROBLAZE_EXCEPTION_FRAME_R17
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swi r18, r1, MICROBLAZE_EXCEPTION_FRAME_R18
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swi r19, r1, MICROBLAZE_EXCEPTION_FRAME_R19
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swi r20, r1, MICROBLAZE_EXCEPTION_FRAME_R20
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swi r21, r1, MICROBLAZE_EXCEPTION_FRAME_R21
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swi r22, r1, MICROBLAZE_EXCEPTION_FRAME_R22
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swi r23, r1, MICROBLAZE_EXCEPTION_FRAME_R23
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swi r24, r1, MICROBLAZE_EXCEPTION_FRAME_R24
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swi r25, r1, MICROBLAZE_EXCEPTION_FRAME_R25
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swi r26, r1, MICROBLAZE_EXCEPTION_FRAME_R26
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swi r27, r1, MICROBLAZE_EXCEPTION_FRAME_R27
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swi r28, r1, MICROBLAZE_EXCEPTION_FRAME_R28
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swi r29, r1, MICROBLAZE_EXCEPTION_FRAME_R29
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swi r30, r1, MICROBLAZE_EXCEPTION_FRAME_R30
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swi r31, r1, MICROBLAZE_EXCEPTION_FRAME_R31
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/* Retrieve and store MSR */
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mfs r3, rmsr
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swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_MSR
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/* Retrieve and store EAR */
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mfs r3, rear
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swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_EAR
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/* Retrieve and store ESR */
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mfs r3, resr
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swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_ESR
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/* Retrieve and store BTR */
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mfs r3, rbtr
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swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_BTR
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/* Calculate and store original stack pointer */
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addik r3, r1, CPU_EXCEPTION_FRAME_SIZE
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swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_R1
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/* set parameter 1 to CPU Exception frame */
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addi r5, r1, 0
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/* call into the debug framework */
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braid _MicroBlaze_Exception_handle
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nop
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