forked from Imagelibrary/rtems
698227e6ea
RTEMS may be booted from a dirty environment. Ensure that FPU trap settings are consistent.
324 lines
7.5 KiB
ArmAsm
324 lines
7.5 KiB
ArmAsm
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSBSPsAArch64Shared
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*
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* @brief Boot and system start code.
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*/
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/*
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* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
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* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <rtems/asm.h>
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#include <rtems/score/percpu.h>
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#include <bspopts.h>
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/* Global symbols */
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.globl _start
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.section ".bsp_start_text", "ax"
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/* Start entry */
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_start:
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/*
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* We do not save the context since we do not return to the boot
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* loader but preserve x1 and x2 to allow access to bootloader parameters
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*/
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#ifndef BSP_START_NEEDS_REGISTER_INITIALIZATION
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mov x5, x1 /* machine type number or ~0 for DT boot */
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mov x6, x2 /* physical address of ATAGs or DTB */
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#else /* BSP_START_NEEDS_REGISTER_INITIALIZATION */
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/*
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* This block is dead code. No aarch64 targets require this. It might be
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* needed for hardware simulations or in future processor variants with
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* lock-step cores.
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*/
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mov x0, XZR
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mov x1, XZR
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mov x2, XZR
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mov x3, XZR
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mov x4, XZR
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mov x5, XZR
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mov x6, XZR
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mov x7, XZR
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mov x8, XZR
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mov x9, XZR
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mov x10, XZR
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mov x11, XZR
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mov x12, XZR
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mov x13, XZR
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mov x14, XZR
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mov x15, XZR
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mov x16, XZR
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mov x17, XZR
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mov x18, XZR
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mov x19, XZR
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mov x20, XZR
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mov x21, XZR
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mov x22, XZR
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mov x23, XZR
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mov x24, XZR
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mov x25, XZR
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mov x26, XZR
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mov x27, XZR
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mov x28, XZR
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mov x29, XZR
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mov x30, XZR
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#ifdef AARCH64_MULTILIB_VFP
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mov CPTR_EL3, XZR
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mov CPTR_EL2, XZR
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mov d0, XZR
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mov d1, XZR
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mov d2, XZR
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mov d3, XZR
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mov d4, XZR
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mov d5, XZR
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mov d6, XZR
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mov d7, XZR
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mov d8, XZR
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mov d9, XZR
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mov d10, XZR
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mov d11, XZR
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mov d12, XZR
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mov d13, XZR
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mov d14, XZR
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mov d15, XZR
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mov d16, XZR
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mov d17, XZR
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mov d18, XZR
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mov d19, XZR
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mov d20, XZR
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mov d21, XZR
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mov d22, XZR
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mov d23, XZR
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mov d24, XZR
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mov d25, XZR
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mov d26, XZR
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mov d27, XZR
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mov d28, XZR
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mov d29, XZR
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mov d30, XZR
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mov d31, XZR
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#endif /* AARCH64_MULTILIB_VFP */
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#endif /* BSP_START_NEEDS_REGISTER_INITIALIZATION */
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/* Initialize SCTLR_EL1 */
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mov x0, XZR
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#if defined(RTEMS_DEBUG)
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/* Enable Stack alignment checking */
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orr x0, x0, #(1<<3)
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#endif
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msr SCTLR_EL1, x0
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mrs x0, CurrentEL
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cmp x0, #(1<<2)
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b.eq _el1_start
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cmp x0, #(2<<2)
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b.eq _el2_start
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_el3_start:
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/*
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* Before leaving the Secure World, we need to initialize the GIC. We
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* do that here in an early stack context in EL3. This will NOT work
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* on secondary core boot! We assume only the primary boot core will
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* start in EL3 if any. Usually on real hardware, we should be running
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* on top of trusted firmware and will not boot in EL3. Qemu fakes it
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* for us and will start the primary core in EL3 and secondary cores
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* will be brought up in EL1NS as expected.
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*/
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#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
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ldr w1, =_ISR_Stack_size
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ldr w2, =_ISR_Stack_area_begin
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#else
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ldr x1, =_ISR_Stack_size
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ldr x2, =_ISR_Stack_area_begin
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#endif
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add x3, x1, x2
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/* using SP0 for the early init stack context at EL3 */
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msr spsel, #0
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mov sp, x3
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/*
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* Invoke the start hook 0.
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* We don't set up exception handling, so this hook better behave.
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*/
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bl bsp_start_hook_0
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/* Drop from EL3 to EL2 */
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/* Initialize HCR_EL2 and SCTLR_EL2 */
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msr HCR_EL2, XZR
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msr SCTLR_EL2, XZR
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/* Set EL2 Execution state via SCR_EL3 */
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mrs x0, SCR_EL3
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/* Set EL2 to AArch64 */
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orr x0, x0, #(1<<10)
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/* Set EL1 to NS */
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orr x0, x0, #1
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msr SCR_EL3, x0
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/* set EL2h mode for eret */
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mov x0, #0b01001
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msr SPSR_EL3, x0
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/* Set EL2 entry point */
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adr x0, _el2_start
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msr ELR_EL3, x0
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eret
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_el2_start:
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/* Drop from EL2 to EL1 */
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/* Configure HCR_EL2 */
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mrs x0, HCR_EL2
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/* Set EL1 Execution state to AArch64 */
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orr x0, x0, #(1<<31)
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/* Disable ID traps */
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bic x0, x0, #(1<<15)
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bic x0, x0, #(1<<16)
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bic x0, x0, #(1<<17)
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bic x0, x0, #(1<<18)
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msr HCR_EL2, x0
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/* Set to EL1h mode for eret */
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mov x0, #0b00101
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msr SPSR_EL2, x0
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/* Set EL1 entry point */
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adr x0, _el1_start
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msr ELR_EL2, x0
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eret
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_el1_start:
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#ifdef RTEMS_SMP
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/* Read MPIDR and get current processor index */
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mrs x7, mpidr_el1
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and x7, x7, #0xff
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#endif
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#ifdef RTEMS_SMP
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/*
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* Get current per-CPU control and store it in PL1 only Thread ID
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* Register (TPIDR_EL1).
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*/
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#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
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ldr w1, =_Per_CPU_Information
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#else
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ldr x1, =_Per_CPU_Information
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#endif
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add x1, x1, x7, lsl #PER_CPU_CONTROL_SIZE_LOG2
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msr TPIDR_EL1, x1
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#endif
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/* Calculate interrupt stack area end for current processor */
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#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
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ldr w1, =_ISR_Stack_size
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#else
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ldr x1, =_ISR_Stack_size
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#endif
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#ifdef RTEMS_SMP
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add x3, x7, #1
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mul x1, x1, x3
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#endif
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#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
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ldr w2, =_ISR_Stack_area_begin
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#else
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ldr x2, =_ISR_Stack_area_begin
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#endif
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add x3, x1, x2
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/* Disable interrupts and debug */
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msr DAIFSet, #0xa
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#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
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mov x8, XZR
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mov x9, XZR
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mov x10, XZR
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mov x11, XZR
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mov x12, XZR
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mov x13, XZR
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mov x14, XZR
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mov x15, XZR
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#endif
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/*
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* SPx: the stack pointer corresponding to the current exception level
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* Normal operation for RTEMS on AArch64 uses SPx and runs on EL1
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* Exception operation (synchronous errors, IRQ, FIQ, System Errors) uses SP0
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*/
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#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
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ldr w1, =bsp_stack_exception_size
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#else
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ldr x1, =bsp_stack_exception_size
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#endif
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/* Switch to SP0 and set exception stack */
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msr spsel, #0
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mov sp, x3
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/* Switch back to SPx for normal operation */
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msr spsel, #1
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sub x3, x3, x1
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/* Set SP1 stack used for normal operation */
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mov sp, x3
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/* Stay in EL1 mode */
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#ifdef AARCH64_MULTILIB_VFP
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#ifdef AARCH64_MULTILIB_HAS_CPACR
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/* Read CPACR */
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mrs x0, CPACR_EL1
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/* Enable EL1 access permissions for CP10 */
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orr x0, x0, #(1 << 20)
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/* Write CPACR */
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msr CPACR_EL1, x0
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isb
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#endif
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/* FPU does not need to be enabled on AArch64 */
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/* Ensure FPU traps are disabled by default */
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mrs x0, FPCR
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bic x0, x0, #((1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12))
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bic x0, x0, #(1 << 15)
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msr FPCR, x0
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#endif /* AARCH64_MULTILIB_VFP */
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/* Branch to start hook 1 */
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bl bsp_start_hook_1
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/* Branch to boot card */
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mov x0, #0
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bl boot_card
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