Sebastian Huber c4c3e68790 bsps/arm: Use fatal error for data cache disable ...

On the Cortex-A cores, at least the L1 data cache is required to provide
support for atomic operations.

Close #5050.

2024-06-25 03:58:34 +00:00

..

cache-cp15.c

bsps/cache: Fix ARM CP-15 get cache size

2024-06-04 15:50:57 +00:00

cache-cp15.h

bsps/arm: Use fatal error for data cache disable

2024-06-25 03:58:34 +00:00

cache-l2c-310.c

bsps/arm: Use fatal error for data cache disable

2024-06-25 03:58:34 +00:00

cache-v7ar-disable-data.S

Update company name

2023-05-20 11:05:26 +02:00

cache-v7m.c

Update company name

2023-05-20 11:05:26 +02:00