forked from Imagelibrary/rtems
92 lines
3.0 KiB
Plaintext
92 lines
3.0 KiB
Plaintext
@c
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@c COPYRIGHT (c) 1988-1998.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c
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@c $Id$
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@c
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@ifinfo
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@node Preface, CPU Model Dependent Features, Top, Top
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@end ifinfo
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@unnumbered Preface
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The Real Time Executive for Multiprocessor Systems
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(RTEMS) is designed to be portable across multiple processor
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architectures. However, the nature of real-time systems makes
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it essential that the application designer understand certain
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processor dependent implementation details. These processor
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dependencies include calling convention, board support package
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issues, interrupt processing, exact RTEMS memory requirements,
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performance data, header files, and the assembly language
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interface to the executive.
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This document discusses the SPARC architecture
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dependencies in this port of RTEMS. Currently, only
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implementations of SPARC Version 7 are supported by RTEMS.
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It is highly recommended that the SPARC RTEMS
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application developer obtain and become familiar with the
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documentation for the processor being used as well as the
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specification for the revision of the SPARC architecture which
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corresponds to that processor.
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@subheading SPARC Architecture Documents
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For information on the SPARC architecture, refer to
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the following documents available from SPARC International, Inc.
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(http://www.sparc.com):
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@itemize @bullet
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@item SPARC Standard Version 7.
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@item SPARC Standard Version 8.
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@item SPARC Standard Version 9.
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@end itemize
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@subheading ERC32 Specific Information
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The European Space Agency's ERC32 is a three chip
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computing core implementing a SPARC V7 processor and associated
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support circuitry for embedded space applications. The integer
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and floating-point units (90C601E & 90C602E) are based on the
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Cypress 7C601 and 7C602, with additional error-detection and
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recovery functions. The memory controller (MEC) implements
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system support functions such as address decoding, memory
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interface, DMA interface, UARTs, timers, interrupt control,
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write-protection, memory reconfiguration and error-detection.
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The core is designed to work at 25MHz, but using space qualified
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memories limits the system frequency to around 15 MHz, resulting
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in a performance of 10 MIPS and 2 MFLOPS.
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Information on the ERC32 and a number of development
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support tools, such as the SPARC Instruction Simulator (SIS),
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are freely available on the Internet. The following documents
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and SIS are available via anonymous ftp or pointing your web
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browser at ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32.
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@itemize @bullet
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@item ERC32 System Design Document
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@item MEC Device Specification
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@end itemize
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Additionally, the SPARC RISC User's Guide from Matra
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MHS documents the functionality of the integer and floating
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point units including the instruction set information. To
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obtain this document as well as ERC32 components and VHDL models
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contact:
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@example
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Matra MHS SA
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3 Avenue du Centre, BP 309,
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78054 St-Quentin-en-Yvelines,
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Cedex, France
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VOICE: +31-1-30607087
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FAX: +31-1-30640693
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@end example
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Amar Guennon (amar.guennon@@matramhs.fr) is familiar with the ERC32.
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