forked from Imagelibrary/rtems
171 lines
3.5 KiB
C
171 lines
3.5 KiB
C
/**
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* @file
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*
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* @ingroup RTEMSBSPsARMLPC24XX_clocks
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*
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* @brief System clocks.
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*/
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/*
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* Copyright (c) 2008-2014 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Obere Lagerstr. 30
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems/counter.h>
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#include <bsp.h>
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#include <bsp/lpc24xx.h>
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#include <bsp/system-clocks.h>
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/**
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* @brief Internal RC oscillator frequency in [Hz].
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*/
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#define LPC24XX_OSCILLATOR_INTERNAL 4000000U
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#ifndef LPC24XX_OSCILLATOR_MAIN
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#error "unknown main oscillator frequency"
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#endif
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#ifndef LPC24XX_OSCILLATOR_RTC
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#error "unknown RTC oscillator frequency"
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#endif
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void lpc24xx_timer_initialize(void)
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{
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/* Reset timer */
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T1TCR = TCR_RST;
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/* Set timer mode */
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T1CTCR = 0;
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/* Set prescaler to zero */
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T1PR = 0;
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/* Reset all interrupt flags */
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T1IR = 0xff;
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/* Do not stop on a match */
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T1MCR = 0;
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/* No captures */
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T1CCR = 0;
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/* Start timer */
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T1TCR = TCR_EN;
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}
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uint32_t _CPU_Counter_frequency(void)
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{
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return LPC24XX_PCLK;
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}
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CPU_Counter_ticks _CPU_Counter_read(void)
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{
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return lpc24xx_timer();
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}
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void lpc24xx_micro_seconds_delay(unsigned us)
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{
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unsigned start = lpc24xx_timer();
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unsigned delay = us * (LPC24XX_PCLK / 1000000);
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unsigned elapsed = 0;
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do {
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elapsed = lpc24xx_timer() - start;
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} while (elapsed < delay);
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}
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#ifdef ARM_MULTILIB_ARCH_V7M
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static unsigned lpc17xx_sysclk(unsigned clksrcsel)
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{
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return (clksrcsel & LPC17XX_SCB_CLKSRCSEL_CLKSRC) != 0 ?
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LPC24XX_OSCILLATOR_MAIN
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: LPC24XX_OSCILLATOR_INTERNAL;
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}
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#endif
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unsigned lpc24xx_pllclk(void)
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{
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#ifdef ARM_MULTILIB_ARCH_V4
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unsigned clksrc = GET_CLKSRCSEL_CLKSRC(CLKSRCSEL);
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unsigned pllinclk = 0;
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unsigned pllclk = 0;
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/* Get PLL input frequency */
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switch (clksrc) {
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case 0:
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pllinclk = LPC24XX_OSCILLATOR_INTERNAL;
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break;
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case 1:
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pllinclk = LPC24XX_OSCILLATOR_MAIN;
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break;
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case 2:
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pllinclk = LPC24XX_OSCILLATOR_RTC;
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break;
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default:
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return 0;
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}
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/* Get PLL output frequency */
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if ((PLLSTAT & PLLSTAT_PLLC) != 0) {
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uint32_t pllcfg = PLLCFG;
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unsigned n = GET_PLLCFG_NSEL(pllcfg) + 1;
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unsigned m = GET_PLLCFG_MSEL(pllcfg) + 1;
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pllclk = (pllinclk / n) * 2 * m;
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} else {
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pllclk = pllinclk;
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}
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#else
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volatile lpc17xx_scb *scb = &LPC17XX_SCB;
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unsigned sysclk = lpc17xx_sysclk(scb->clksrcsel);
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unsigned pllstat = scb->pll_0.stat;
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unsigned pllclk = 0;
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unsigned enabled_and_locked = LPC17XX_PLL_STAT_PLLE
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| LPC17XX_PLL_STAT_PLOCK;
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if ((pllstat & enabled_and_locked) == enabled_and_locked) {
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unsigned m = LPC17XX_PLL_SEL_MSEL_GET(pllstat) + 1;
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pllclk = sysclk * m;
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}
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#endif
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return pllclk;
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}
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unsigned lpc24xx_cclk(void)
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{
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#ifdef ARM_MULTILIB_ARCH_V4
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/* Get PLL output frequency */
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unsigned pllclk = lpc24xx_pllclk();
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/* Get CPU frequency */
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unsigned cclk = pllclk / (GET_CCLKCFG_CCLKSEL(CCLKCFG) + 1);
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#else
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volatile lpc17xx_scb *scb = &LPC17XX_SCB;
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unsigned cclksel = scb->cclksel;
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unsigned cclk_in = 0;
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unsigned cclk = 0;
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if ((cclksel & LPC17XX_SCB_CCLKSEL_CCLKSEL) != 0) {
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cclk_in = lpc24xx_pllclk();
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} else {
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cclk_in = lpc17xx_sysclk(scb->clksrcsel);
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}
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cclk = cclk_in / LPC17XX_SCB_CCLKSEL_CCLKDIV_GET(cclksel);
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#endif
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return cclk;
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}
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