forked from Imagelibrary/rtems
022851aba5
Tested and implemented on ARM, m68k, PowerPC and SPARC. Other architectures need more work.
109 lines
3.5 KiB
Perl
109 lines
3.5 KiB
Perl
@c
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@c COPYRIGHT (c) 1988-2002.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@ifinfo
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@end ifinfo
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@chapter V850 Specific Information
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This chapter discusses the
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@uref{http://en.wikipedia.org/wiki/V850,V850 architecture}
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dependencies in this port of RTEMS. The V850 was originally manufactured
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by NEC but is now part of the Renesas Electronics product line.
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@subheading Architecture Documents
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For information on the V850 architecture refer to the
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@uref{http://am.renesas.com/products/mpumcu/v850/index.jsp,Renesas v850 product page}.
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@section CPU Model Dependent Features
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This section presents the set of features which vary across V850 implementations and are of importance to RTEMS. The set of CPU model feature macros are defined in the file @file{cpukit/score/cpu/v850/rtems/score/v850.h} based upon the particular CPU
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model flags specified on the compilation command line.
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@subsection CPU Model Name
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The macro @code{CPU_MODEL_NAME} is a string which designates
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the architectural level of this CPU model. See in
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@file{cpukit/score/cpu/v850/rtems/score/v850.h} for the values.
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@subsection Count Leading Zeroes Instruction
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The V850v5 and later has the count leading zeroes @code{clz} instruction which
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could be used to speed up the find first bit operation. The use of this
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instruction should significantly speed up the scheduling associated with a
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thread blocking. This is currently not used.
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@subsection Floating Point Unit
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A floating point unit is currently not supported.
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@section Calling Conventions
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Please refer to the
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@uref{http://www.filibeto.org/unix/tru64/lib/ossc/doc/cygnus_doc-99r1/html/6_embed/embV850.html,
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Procedure Call Standard for the V850 Architecture} or the GCC source
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code for detailed information on the calling conventions.
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@subsection Register Usage
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Fixed registers are never available for register allocation in the
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compiler. By default the following registers are fixed in GCC:
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@itemize @bullet
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@item r0 (zero)
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@item r3 (sp)
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@item r4 (gp)
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@item r30 (ep)
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@end itemize
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@c r1 is mentioned as special purpose but I do not see a purpose
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Caller saved registers can be used by the compiler to hold values that
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do not live across function calls. The caller saved registers are r2,
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r5 through r19, and r31.
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Callee saved registers retain their value across function calls. The
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callee saved registers are r20 through r29.
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r6 through r9 are parameter registers while r10 and r11 are function return registers. r31 is the return pointer.
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r29 is used as the frame pointer in some functions.
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@section Memory Model
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A flat 32-bit memory model is supported.
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@section Interrupt Processing
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The V850 architecture has ...
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@subsection Interrupt Levels
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The RTEMS interrupt level mapping scheme for the V850 is very simple. If
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the requested interrupt level is 1, then interrupts are disabled in the
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PSW register using the @code{di} instruction. If the requested interrupt
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level is 0, then interrupts are enabled in the PSW register using the
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@code{ei} instruction or restoring the previous value of the PSW register.
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@subsection Interrupt Stack
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The board support package must initialize the interrupt stack. The memory for
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the stacks is usually reserved in the linker script.
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@section Default Fatal Error Processing
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The default fatal error handler for this architecture performs the
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following actions:
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@itemize @bullet
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@item disables operating system supported interrupts (IRQ),
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@item places the error code in @code{r10}, and
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@item executes a halt processor instruction.
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@end itemize
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@section Thread-Local Storage
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Thread-local storage is not implemented.
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