forked from Imagelibrary/rtems
8dcbc16b6e
Here is a patch which slightly improves the i386 interrupt handling
macros. These macros were written to use both input and output
parameters, which is not necessary. This patch changes them to use
only an input or output parameter, as appropriate. It also changes
the constraints to permit the interrupt level to be loaded directly in
and out of memory, rather than always requiring a register.
516 lines
13 KiB
C
516 lines
13 KiB
C
/*
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* cpu.h - This file contains definitions for data structure related
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* to Intel system programming. More information can be found
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* on Intel site and more precisely in the following book :
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*
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* Pentium Processor familly
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* Developper's Manual
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*
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* Volume 3 : Architecture and Programming Manual
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*
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* Copyright (C) 1998 Eric Valette (valette@crf.canon.fr)
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* Canon Centre Recherche France.
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*
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* The license and distribution terms for this file may be
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* found in found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* $Id$
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*/
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#ifndef _LIBCPU_i386_CPU_H
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#define _LIBCPU_i386_CPU_H
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#include <libcpu/registers.h>
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#ifndef ASM
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/*
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* Interrupt Level Macros
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*/
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#define i386_disable_interrupts( _level ) \
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{ \
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_level = 0; /* avoids warnings */ \
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asm volatile ( "pushf ; \
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cli ; \
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pop %0" \
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: "=rm" ((_level)) \
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); \
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}
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#define i386_enable_interrupts( _level ) \
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{ \
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asm volatile ( "push %0 ; \
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popf" \
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: "=rm" ((_level)) \
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); \
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}
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#define i386_flash_interrupts( _level ) \
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{ \
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asm volatile ( "push %0 ; \
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popf ; \
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cli" \
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: "=rm" ((_level)) \
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); \
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}
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#define i386_get_interrupt_level( _level ) \
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do { \
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register unsigned32 _eflags; \
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\
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asm volatile ( "pushf ; \
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pop %0" \
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: "=rm" ((_eflags)) \
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); \
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\
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_level = (_eflags & EFLAGS_INTR_ENABLE) ? 0 : 1; \
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} while (0)
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#define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level )
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#define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level )
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/*
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* Segment Access Routines
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*
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* NOTE: Unfortunately, these are still static inlines even when the
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* "macro" implementation of the generic code is used.
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*/
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static inline unsigned short i386_get_cs()
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{
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register unsigned short segment = 0;
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asm volatile ( "movw %%cs,%0" : "=r" (segment) : "0" (segment) );
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return segment;
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}
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static inline unsigned short i386_get_ds()
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{
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register unsigned short segment = 0;
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asm volatile ( "movw %%ds,%0" : "=r" (segment) : "0" (segment) );
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return segment;
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}
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static inline unsigned short i386_get_es()
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{
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register unsigned short segment = 0;
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asm volatile ( "movw %%es,%0" : "=r" (segment) : "0" (segment) );
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return segment;
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}
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static inline unsigned short i386_get_ss()
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{
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register unsigned short segment = 0;
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asm volatile ( "movw %%ss,%0" : "=r" (segment) : "0" (segment) );
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return segment;
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}
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static inline unsigned short i386_get_fs()
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{
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register unsigned short segment = 0;
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asm volatile ( "movw %%fs,%0" : "=r" (segment) : "0" (segment) );
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return segment;
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}
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static inline unsigned short i386_get_gs()
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{
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register unsigned short segment = 0;
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asm volatile ( "movw %%gs,%0" : "=r" (segment) : "0" (segment) );
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return segment;
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}
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/*
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* Added for pagination management
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*/
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static inline unsigned int i386_get_cr0()
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{
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register unsigned int segment = 0;
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asm volatile ( "movl %%cr0,%0" : "=r" (segment) : "0" (segment) );
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return segment;
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}
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static inline void i386_set_cr0(unsigned int segment)
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{
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asm volatile ( "movl %0,%%cr0" : "=r" (segment) : "0" (segment) );
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}
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static inline unsigned int i386_get_cr2()
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{
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register unsigned int segment = 0;
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asm volatile ( "movl %%cr2,%0" : "=r" (segment) : "0" (segment) );
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return segment;
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}
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static inline unsigned int i386_get_cr3()
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{
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register unsigned int segment = 0;
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asm volatile ( "movl %%cr3,%0" : "=r" (segment) : "0" (segment) );
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return segment;
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}
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static inline void i386_set_cr3(unsigned int segment)
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{
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asm volatile ( "movl %0,%%cr3" : "=r" (segment) : "0" (segment) );
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}
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/*
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* IO Port Access Routines
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*/
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#define i386_outport_byte( _port, _value ) \
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{ register unsigned short __port = _port; \
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register unsigned char __value = _value; \
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\
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asm volatile ( "outb %0,%1" : "=a" (__value), "=d" (__port) \
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: "0" (__value), "1" (__port) \
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); \
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}
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#define i386_outport_word( _port, _value ) \
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{ register unsigned short __port = _port; \
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register unsigned short __value = _value; \
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\
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asm volatile ( "outw %0,%1" : "=a" (__value), "=d" (__port) \
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: "0" (__value), "1" (__port) \
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); \
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}
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#define i386_outport_long( _port, _value ) \
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{ register unsigned short __port = _port; \
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register unsigned int __value = _value; \
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\
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asm volatile ( "outl %0,%1" : "=a" (__value), "=d" (__port) \
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: "0" (__value), "1" (__port) \
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); \
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}
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#define i386_inport_byte( _port, _value ) \
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{ register unsigned short __port = _port; \
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register unsigned char __value = 0; \
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\
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asm volatile ( "inb %1,%0" : "=a" (__value), "=d" (__port) \
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: "0" (__value), "1" (__port) \
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); \
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_value = __value; \
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}
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#define i386_inport_word( _port, _value ) \
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{ register unsigned short __port = _port; \
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register unsigned short __value = 0; \
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\
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asm volatile ( "inw %1,%0" : "=a" (__value), "=d" (__port) \
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: "0" (__value), "1" (__port) \
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); \
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_value = __value; \
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}
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#define i386_inport_long( _port, _value ) \
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{ register unsigned short __port = _port; \
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register unsigned int __value = 0; \
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\
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asm volatile ( "inl %1,%0" : "=a" (__value), "=d" (__port) \
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: "0" (__value), "1" (__port) \
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); \
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_value = __value; \
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}
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/*
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* Type definition for raw interrupts.
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*/
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typedef unsigned char rtems_vector_offset;
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struct __rtems_raw_irq_connect_data__;
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typedef void (*rtems_raw_irq_hdl) (void);
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typedef void (*rtems_raw_irq_enable) (const struct __rtems_raw_irq_connect_data__*);
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typedef void (*rtems_raw_irq_disable) (const struct __rtems_raw_irq_connect_data__*);
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typedef int (*rtems_raw_irq_is_enabled) (const struct __rtems_raw_irq_connect_data__*);
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typedef struct __rtems_raw_irq_connect_data__{
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/*
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* IDT vector offset (IRQ line + PC386_IRQ_VECTOR_BASE)
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*/
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rtems_vector_offset idtIndex;
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/*
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* IDT raw handler. See comment on handler properties below in function prototype.
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*/
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rtems_raw_irq_hdl hdl;
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/*
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* function for enabling raw interrupts. In order to be consistent
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* with the fact that the raw connexion can defined in the
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* libcpu library, this library should have no knowledge of
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* board specific hardware to manage interrupts and thus the
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* "on" routine must enable the irq both at device and PIC level.
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*
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*/
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rtems_raw_irq_enable on;
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/*
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* function for disabling raw interrupts. In order to be consistent
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* with the fact that the raw connexion can defined in the
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* libcpu library, this library should have no knowledge of
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* board specific hardware to manage interrupts and thus the
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* "on" routine must disable the irq both at device and PIC level.
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*
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*/
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rtems_raw_irq_disable off;
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/*
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* function enabling to know what interrupt may currently occur
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*/
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rtems_raw_irq_is_enabled isOn;
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}rtems_raw_irq_connect_data;
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typedef struct {
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/*
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* size of all the table fields (*Tbl) described below.
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*/
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unsigned int idtSize;
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/*
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* Default handler used when disconnecting interrupts.
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*/
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rtems_raw_irq_connect_data defaultRawEntry;
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/*
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* Table containing initials/current value.
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*/
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rtems_raw_irq_connect_data* rawIrqHdlTbl;
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}rtems_raw_irq_global_settings;
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/*
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* See page 14.9 Figure 14-2.
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*
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*/
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typedef struct {
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unsigned int low_offsets_bits : 16;
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unsigned int segment_selector : 16;
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unsigned int fixed_value_bits : 8;
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unsigned int gate_type : 5;
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unsigned int privilege : 2;
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unsigned int present : 1;
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unsigned int high_offsets_bits: 16;
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}interrupt_gate_descriptor;
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/*
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* C callable function enabling to create a interrupt_gate_descriptor
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*/
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void create_interrupt_gate_descriptor (interrupt_gate_descriptor*, rtems_raw_irq_hdl);
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/*
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* C callable function enabling to get handler currently connected to a vector
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*
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*/
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rtems_raw_irq_hdl get_hdl_from_vector(rtems_vector_offset);
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/*
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* C callable function enabling to get easilly usable info from
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* the actual value of IDT register.
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*/
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extern void i386_get_info_from_IDTR (interrupt_gate_descriptor** table,
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unsigned* limit);
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/*
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* C callable function enabling to change the value of IDT register. Must be called
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* with interrupts masked at processor level!!!.
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*/
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extern void i386_set_IDTR (interrupt_gate_descriptor* table,
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unsigned limit);
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/*
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* C callable function enabling to set up one raw idt entry
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*/
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extern int i386_set_idt_entry (const rtems_raw_irq_connect_data*);
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/*
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* C callable function enabling to get one current raw idt entry
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*/
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extern int i386_get_current_idt_entry (rtems_raw_irq_connect_data*);
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/*
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* C callable function enabling to remove one current raw idt entry
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*/
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extern int i386_delete_idt_entry (const rtems_raw_irq_connect_data*);
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/*
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* C callable function enabling to init idt.
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*
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* CAUTION : this function assumes that the IDTR register
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* has been already set.
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*/
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extern int i386_init_idt (rtems_raw_irq_global_settings* config);
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/*
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* C callable function enabling to get actual idt configuration
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*/
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extern int i386_get_idt_config (rtems_raw_irq_global_settings** config);
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/*
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* See page 11.12 Figure 11-8.
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*
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*/
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typedef struct {
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unsigned int limit_15_0 : 16;
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unsigned int base_address_15_0 : 16;
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unsigned int base_address_23_16 : 8;
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unsigned int type : 4;
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unsigned int descriptor_type : 1;
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unsigned int privilege : 2;
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unsigned int present : 1;
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unsigned int limit_19_16 : 4;
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unsigned int available : 1;
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unsigned int fixed_value_bits : 1;
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unsigned int operation_size : 1;
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unsigned int granularity : 1;
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unsigned int base_address_31_24 : 8;
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}segment_descriptors;
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/*
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* C callable function enabling to get easilly usable info from
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* the actual value of GDT register.
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*/
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extern void i386_get_info_from_GDTR (segment_descriptors** table,
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unsigned* limit);
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/*
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* C callable function enabling to change the value of GDT register. Must be called
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* with interrupts masked at processor level!!!.
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*/
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extern void i386_set_GDTR (segment_descriptors*,
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unsigned limit);
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/*
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* C callable function enabling to set up one raw interrupt handler
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*/
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extern int i386_set_gdt_entry (unsigned short segment_selector, unsigned base,
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unsigned limit);
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/*
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* See page 11.18 Figure 11-12.
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*
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*/
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typedef struct {
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unsigned int offset : 12;
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unsigned int page : 10;
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unsigned int directory : 10;
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}la_bits;
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typedef union {
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la_bits bits;
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unsigned int address;
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}linear_address;
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/*
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* See page 11.20 Figure 11-14.
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*
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*/
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typedef struct {
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unsigned int present : 1;
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unsigned int writable : 1;
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unsigned int user : 1;
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unsigned int write_through : 1;
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unsigned int cache_disable : 1;
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unsigned int accessed : 1;
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unsigned int reserved1 : 1;
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unsigned int page_size : 1;
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unsigned int reserved2 : 1;
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unsigned int available : 3;
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unsigned int page_frame_address : 20;
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}page_dir_bits;
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typedef union {
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page_dir_bits bits;
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unsigned int dir_entry;
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}page_dir_entry;
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typedef struct {
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unsigned int present : 1;
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unsigned int writable : 1;
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unsigned int user : 1;
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unsigned int write_through : 1;
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unsigned int cache_disable : 1;
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unsigned int accessed : 1;
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unsigned int dirty : 1;
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unsigned int reserved2 : 2;
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unsigned int available : 3;
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unsigned int page_frame_address : 20;
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}page_table_bits;
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typedef union {
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page_table_bits bits;
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unsigned int table_entry;
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}page_table_entry;
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/*
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* definitions related to page table entry
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*/
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#define PG_SIZE 0x1000
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#define MASK_OFFSET 0xFFF
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#define MAX_ENTRY (PG_SIZE/sizeof(page_dir_entry))
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#define FOUR_MB 0x400000
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#define MASK_FLAGS 0x1A
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#define PTE_PRESENT 0x01
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#define PTE_WRITABLE 0x02
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#define PTE_USER 0x04
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#define PTE_WRITE_THROUGH 0x08
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#define PTE_CACHE_DISABLE 0x10
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typedef struct {
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page_dir_entry pageDirEntry[MAX_ENTRY];
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}page_directory;
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typedef struct {
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page_table_entry pageTableEntry[MAX_ENTRY];
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}page_table;
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static inline void flush_cache(){
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asm volatile ("wbinvd");
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}
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/* C declaration for paging management */
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extern int _CPU_is_cache_enabled();
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extern int _CPU_is_paging_enabled();
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extern int init_paging();
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extern void _CPU_enable_paging();
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extern void _CPU_disable_paging();
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extern void _CPU_disable_cache();
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extern void _CPU_enable_cache();
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extern int _CPU_map_phys_address
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(void **mappedAddress, void *physAddress,
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int size, int flag);
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extern int _CPU_unmap_virt_address (void *mappedAddress, int size);
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extern int _CPU_change_memory_mapping_attribute
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(void **newAddress, void *mappedAddress,
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unsigned int size, unsigned int flag);
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extern int _CPU_display_memory_attribute();
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# endif /* ASM */
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#endif
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