forked from Imagelibrary/rtems
8536b67bab
Putting the duart in libcpu was very optimistic and presumptuous. It has never been used again on another SoC and is BSP specific.
258 lines
7.0 KiB
C
258 lines
7.0 KiB
C
/**
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* @file
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*
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* ISR Vectoring support for the Synova Mongoose-V.
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*/
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/*
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* COPYRIGHT (c) 1989-2012.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems.h>
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#include <stdlib.h>
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#include <bsp/mongoose-v.h>
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#include <rtems/mips/iregdef.h>
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#include <rtems/mips/idtcpu.h>
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#include <rtems/irq.h>
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#include <bsp/irq.h>
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#include <bsp/irq-generic.h>
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#include <rtems/bspIo.h> /* for printk */
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int mips_default_isr( int vector );
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int assertSoftwareInterrupt( uint32_t n );
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void mips_vector_isr_handlers( CPU_Interrupt_frame *frame );
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int mips_default_isr( int vector )
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{
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unsigned int sr, sr2;
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unsigned int cause;
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mips_get_sr( sr );
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mips_get_cause( cause );
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sr2 = sr & ~0xffff;
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mips_set_sr(sr2);
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printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n", vector, cause, sr );
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rtems_fatal_error_occurred(1);
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return 0;
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}
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/* userspace routine to assert either software interrupt */
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int assertSoftwareInterrupt( uint32_t n )
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{
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if( n<2 )
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{
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uint32_t c;
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mips_get_cause(c);
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c = ((n+1) << CAUSE_IPSHIFT);
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mips_set_cause(c);
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return n;
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}
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else return -1;
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}
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/*
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* Instrumentation tweaks for isr timing measurement, turning them off
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* via this #if will remove the code entirely from the RTEMS kernel.
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*/
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#if 0
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#define SET_ISR_FLAG( offset ) *((uint32_t*)(0x8001e000+offset)) = 1;
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#define CLR_ISR_FLAG( offset ) *((uint32_t*)(0x8001e000+offset)) = 0;
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#else
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#define SET_ISR_FLAG( offset )
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#define CLR_ISR_FLAG( offset )
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#endif
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static volatile uint32_t _ivcause, _ivsr;
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static uint32_t READ_CAUSE(void)
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{
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mips_get_cause( _ivcause );
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_ivcause &= SR_IMASK; /* mask off everything other than the interrupt bits */
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return ((_ivcause & (_ivsr & SR_IMASK)) >> CAUSE_IPSHIFT);
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}
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/*
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* This rather strangely coded routine enforces an interrupt priority
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* scheme. As it runs thru finding whichever interrupt caused it to get
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* here, it test for other interrupts arriving in the meantime (maybe it
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* occured while the vector code is executing for instance). Each new
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* interrupt will be served in order of its priority. In an effort to
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* minimize overhead, the cause register is only fetched after an
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* interrupt is serviced. Because of the intvect goto's, this routine
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* will only exit when all interrupts have been serviced and no more
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* have arrived, this improves interrupt latency at the cost of
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* increasing scheduling jitter; though scheduling jitter should only
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* become apparent in high interrupt load conditions.
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*/
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void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
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{
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uint32_t cshifted;
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/* mips_get_sr( sr ); */
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_ivsr = frame->c0_sr;
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cshifted = READ_CAUSE();
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intvect:
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if( cshifted & 0x3 )
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{
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/* making the software interrupt the highest priority is kind of
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* stupid, but it makes the bit testing lots easier. On the other
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* hand, these ints are infrequently used and the testing overhead
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* is minimal. Who knows, high-priority software ints might be
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* handy in some situation.
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*/
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/* unset both software int cause bits */
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mips_set_cause( _ivcause & ~(3 << CAUSE_IPSHIFT) );
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if ( cshifted & 0x01 ) /* SW[0] */
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{
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bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_SOFTWARE_1 );
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}
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if ( cshifted & 0x02 ) /* SW[1] */
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{
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bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_SOFTWARE_2 );
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}
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cshifted = READ_CAUSE();
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}
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if ( cshifted & 0x04 ) /* IP[0] ==> INT0 == TIMER1 */
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{
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SET_ISR_FLAG( 0x4 );
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bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_TIMER1 );
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CLR_ISR_FLAG( 0x4 );
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if( (cshifted = READ_CAUSE()) & 0x3 ) goto intvect;
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}
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if ( cshifted & 0x08 ) /* IP[1] ==> INT1 == TIMER2*/
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{
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SET_ISR_FLAG( 0x8 );
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bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_TIMER2 );
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CLR_ISR_FLAG( 0x8 );
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if( (cshifted = READ_CAUSE()) & 0x7 ) goto intvect;
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}
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if ( cshifted & 0x10 ) /* IP[2] ==> INT2 */
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{
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SET_ISR_FLAG( 0x10 );
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bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_INT2 );
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CLR_ISR_FLAG( 0x10 );
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if( (cshifted = READ_CAUSE()) & 0xf ) goto intvect;
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}
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if ( cshifted & 0x20 ) /* IP[3] ==> INT3 == FPU interrupt */
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{
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SET_ISR_FLAG( 0x20 );
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bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_INT3 );
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CLR_ISR_FLAG( 0x20 );
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if( (cshifted = READ_CAUSE()) & 0x1f ) goto intvect;
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}
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if ( cshifted & 0x40 ) /* IP[4] ==> INT4, external interrupt */
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{
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SET_ISR_FLAG( 0x40 );
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bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_INT4 );
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CLR_ISR_FLAG( 0x40 );
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if( (cshifted = READ_CAUSE()) & 0x3f ) goto intvect;
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}
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if ( cshifted & 0x80 ) /* IP[5] ==> INT5, peripheral interrupt */
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{
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uint32_t bit;
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uint32_t pf_icr, pf_mask, pf_reset = 0;
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uint32_t i, m;
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pf_icr = MONGOOSEV_READ( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER );
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/*
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for (bit=0, pf_mask = 1; bit < 32; bit++, pf_mask <<= 1 )
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{
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if ( pf_icr & pf_mask )
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{
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SET_ISR_FLAG( 0x80 + (bit*4) );
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bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_PERIPHERAL_BASE + bit );
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CLR_ISR_FLAG( 0x80 + (bit*4) );
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pf_reset |= pf_mask;
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if( (cshifted = READ_CAUSE()) & 0xff ) break;
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}
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}
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*/
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/*
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* iterate thru 32 bits in 4 chunks of 8 bits each. This lets us
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* quickly get past unasserted interrupts instead of flogging our
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* way thru a full 32 bits. pf_mask shifts left 8 bits at a time
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* to serve as a interrupt cause test mask.
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*/
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for( bit=0, pf_mask = 0xff; (bit < 32 && pf_icr); (bit+=8, pf_mask <<= 8) )
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{
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if ( pf_icr & pf_mask )
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{
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/* one or more of the 8 bits we're testing is high */
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m = (1 << bit);
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/* iterate thru the 8 bits, servicing any of the interrupts */
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for(i=0; (i<8 && pf_icr); (i++, m <<= 1))
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{
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if( pf_icr & m )
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{
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SET_ISR_FLAG( 0x80 + ((bit + i) * 4) );
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bsp_interrupt_handler_dispatch( MONGOOSEV_IRQ_PERIPHERAL_BASE + bit + i );
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CLR_ISR_FLAG( 0x80 + ((bit + i) * 4) );
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/* or each serviced interrupt into our interrupt clear mask */
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pf_reset |= m;
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/* xor off each int we service so we can immediately
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* exit once we get the last one
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*/
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pf_icr %= m;
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/* if another interrupt has arrived, jump out right
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* away but be sure to reset all the interrupts we've
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* already serviced
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*/
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if( READ_CAUSE() & 0xff ) goto pfexit;
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}
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}
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}
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}
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pfexit:
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MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_STATUS_REGISTER, pf_reset );
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}
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/*
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* this is a last ditch interrupt check, if an interrupt arrives
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* after this step, servicing it will incur the entire interrupt
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* overhead cost.
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*/
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if( (cshifted = READ_CAUSE()) & 0xff ) goto intvect;
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}
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