Sebastian Huber 20d82377a6 arm: Fix arm_cp15_set_translation_table_entries() ...

In a multi-processor system we must broadcast the TLB maintenance operation to
the Inner Shareable domain to ensure that the other processors update their TLB
caches accordingly.

Close #4068.

2020-09-17 08:20:35 +02:00

..

cache

bsps: Adjust shared Doxygen groups

2019-03-08 07:42:54 +01:00

clock

bsps/arm: Fix uninitialized value in generic timer

2020-04-20 09:07:35 +02:00

cp15

arm: Fix arm_cp15_set_translation_table_entries()

2020-09-17 08:20:35 +02:00

cpucounter

arm: Simplify CPU counter support

2018-06-15 13:12:05 +02:00

fb

bsps: Move arm-pl111-fb.c to bsps

2018-04-24 10:24:29 +02:00

irq

arm: ARMv7-M statically initialized vector table

2020-04-03 09:12:44 +02:00

net

network: Use kernel/user space header files

2018-09-10 10:38:44 +02:00

serial

bsp/xilinx-zynq: Flush TX-Buffer before initializing uart

2020-08-22 17:29:25 +10:00

start

bsps/arm: Use _Assert()

2020-08-20 14:54:18 +02:00

doxygen.h

bsps/arm: Adjust CMSIS Doxygen groups

2019-03-08 07:42:54 +01:00