forked from Imagelibrary/rtems
103 lines
2.3 KiB
C
103 lines
2.3 KiB
C
/**
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* @file
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*
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* @brief LM32 CPU Dependent Source
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*/
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/*
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*
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* Jukka Pietarinen <jukka.pietarinen@mrf.fi>, 2008,
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* Micro-Research Finland Oy
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <rtems/score/cpuimpl.h>
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#include <rtems/score/isr.h>
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/* _CPU_Initialize
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*
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* This routine performs processor dependent initialization.
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*
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* INPUT PARAMETERS: NONE
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*
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* LM32 Specific Information:
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*
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* XXX document implementation including references if appropriate
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*/
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void _CPU_Initialize(void)
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{
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/*
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* If there is not an easy way to initialize the FP context
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* during Context_Initialize, then it is usually easier to
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* save an "uninitialized" FP context here and copy it to
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* the task's during Context_Initialize.
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*/
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/* FP context initialization support goes here */
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}
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uint32_t _CPU_ISR_Get_level( void )
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{
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/*
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* This routine returns the current interrupt level.
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*/
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return 0;
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}
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void _CPU_ISR_install_vector(
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uint32_t vector,
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CPU_ISR_handler new_handler,
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CPU_ISR_handler *old_handler
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)
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{
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*old_handler = _ISR_Vector_table[ vector ];
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/*
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* We put the actual user ISR address in '_ISR_vector_table'. This will
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* be used by the _ISR_Handler so the user gets control.
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*/
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_ISR_Vector_table[ vector ] = new_handler;
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}
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/*
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* _CPU_Thread_Idle_body
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*
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* NOTES:
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*
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* 1. This is the same as the regular CPU independent algorithm.
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*
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* 2. If you implement this using a "halt", "idle", or "shutdown"
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* instruction, then don't forget to put it in an infinite loop.
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*
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* 3. Be warned. Some processors with onboard DMA have been known
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* to stop the DMA if the CPU were put in IDLE mode. This might
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* also be a problem with other on-chip peripherals. So use this
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* hook with caution.
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*
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* LM32 Specific Information:
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*
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* XXX document implementation including references if appropriate
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*/
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void *_CPU_Thread_Idle_body( uintptr_t ignored )
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{
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for( ; ; ) {
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/* The LM32 softcore itself hasn't any HLT instruction. But the
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* LM32 qemu target interprets this nop instruction as HLT.
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*/
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__asm__ volatile("and r0, r0, r0");
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}
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}
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