forked from Imagelibrary/rtems
156 lines
3.4 KiB
C
156 lines
3.4 KiB
C
/*
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* Intel i960CA Dependent Source
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*
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*
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* COPYRIGHT (c) 1989-1998.
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* On-Line Applications Research Corporation (OAR).
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* Copyright assigned to U.S. Government, 1994.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* $Id$
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*/
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#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
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#else
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#warning "*** ENTIRE FILE IMPLEMENTED & TESTED FOR CA ONLY ***"
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#warning "*** THIS FILE WILL NOT COMPILE ON ANOTHER FAMILY MEMBER ***"
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#endif
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#include <rtems/system.h>
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#include <rtems/score/isr.h>
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/* _CPU_Initialize
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*
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* This routine performs processor dependent initialization.
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*
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* INPUT PARAMETERS:
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* cpu_table - CPU table to initialize
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* thread_dispatch - address of disptaching routine
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*
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* OUTPUT PARAMETERS: NONE
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*/
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void _CPU_Initialize(
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rtems_cpu_table *cpu_table,
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void (*thread_dispatch) /* ignored on this CPU */
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)
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{
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_CPU_Table = *cpu_table;
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}
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/*PAGE
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*
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* _CPU_ISR_Get_level
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*/
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unsigned32 _CPU_ISR_Get_level( void )
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{
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unsigned32 level;
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i960_get_interrupt_level( level );
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return level;
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}
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/*PAGE
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*
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* _CPU_ISR_install_raw_handler
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*/
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#define _Is_vector_caching_enabled( _prcb ) \
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((_prcb)->control_tbl->icon & 0x2000)
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void _CPU_ISR_install_raw_handler(
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unsigned32 vector,
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proc_ptr new_handler,
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proc_ptr *old_handler
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)
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{
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i960ca_PRCB *prcb = _CPU_Table.Prcb;
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proc_ptr *cached_intr_tbl = NULL;
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/* The i80960CA does not support vectors 0-7. The first 9 entries
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* in the Interrupt Table are used to manage pending interrupts.
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* Thus vector 8, the first valid vector number, is actually in
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* slot 9 in the table.
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*/
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*old_handler = prcb->intr_tbl[ vector + 1 ];
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prcb->intr_tbl[ vector + 1 ] = new_handler;
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if ( _Is_vector_caching_enabled( prcb ) )
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if ( (vector & 0xf) == 0x2 ) /* cacheable? */
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cached_intr_tbl[ vector >> 4 ] = new_handler;
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}
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/*PAGE
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*
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* _CPU__ISR_install_vector
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*
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* Install the RTEMS vector wrapper in the CPU's interrupt table.
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*
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* Input parameters:
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* vector - interrupt vector number
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* old_handler - former ISR for this vector number
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* new_handler - replacement ISR for this vector number
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*
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* Output parameters: NONE
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*
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*/
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void _CPU_ISR_install_vector(
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unsigned32 vector,
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proc_ptr new_handler,
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proc_ptr *old_handler
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)
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{
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proc_ptr ignored;
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*old_handler = _ISR_Vector_table[ vector ];
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_CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
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_ISR_Vector_table[ vector ] = new_handler;
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}
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/*PAGE
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*
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* _CPU_Install_interrupt_stack
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*/
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#define soft_reset( prcb ) \
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{ register i960ca_PRCB *_prcb = (prcb); \
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register unsigned32 *_next=0; \
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register unsigned32 _cmd = 0x30000; \
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asm volatile( "lda next,%1; \
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sysctl %0,%1,%2; \
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next: mov g0,g0" \
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: "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
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: "0" (_cmd), "1" (_next), "2" (_prcb) ); \
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}
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void _CPU_Install_interrupt_stack( void )
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{
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i960ca_PRCB *prcb = _CPU_Table.Prcb;
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unsigned32 level;
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/*
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* Set the Interrupt Stack in the PRCB and force a reload of it.
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* Interrupts are disabled for safety.
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*/
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_CPU_ISR_Disable( level );
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prcb->intr_stack = _CPU_Interrupt_stack_low;
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soft_reset( prcb );
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_CPU_ISR_Enable( level );
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}
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