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111 lines
3.8 KiB
Perl
111 lines
3.8 KiB
Perl
@c
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@c COPYRIGHT (c) 1988-2002.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c
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@c $Id$
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@c
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@chapter Memory Model
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@section Introduction
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A processor may support any combination of memory
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models ranging from pure physical addressing to complex demand
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paged virtual memory systems. RTEMS supports a flat memory
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model which ranges contiguously over the processor's allowable
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address space. RTEMS does not support segmentation or virtual
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memory of any kind. The appropriate memory model for RTEMS
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provided by the targeted processor and related characteristics
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of that model are described in this chapter.
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@section Flat Memory Model
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The PowerPC architecture supports a variety of memory models.
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RTEMS supports the PowerPC using a flat memory model with
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paging disabled. In this mode, the PowerPC automatically
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converts every address from a logical to a physical address
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each time it is used. The PowerPC uses information provided
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in the Block Address Translation (BAT) to convert these addresses.
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Implementations of the PowerPC architecture may be thirty-two or sixty-four bit.
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The PowerPC architecture supports a flat thirty-two or sixty-four bit address
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space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4
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gigabytes) in thirty-two bit implementations or to 0xFFFFFFFFFFFFFFFF
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in sixty-four bit implementations. Each address is represented
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by either a thirty-two bit or sixty-four bit value and is byte addressable.
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The address may be used to reference a single byte, half-word
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(2-bytes), word (4 bytes), or in sixty-four bit implementations a
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doubleword (8 bytes). Memory accesses within the address space are
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performed in big or little endian fashion by the PowerPC based
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upon the current setting of the Little-endian mode enable bit (LE)
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in the Machine State Register (MSR). While the processor is in
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big endian mode, memory accesses which are not properly aligned
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generate an "alignment exception" (vector offset 0x00600). In
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little endian mode, the PowerPC architecture does not require
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the processor to generate alignment exceptions.
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The following table lists the alignment requirements for a variety
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of data accesses:
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@ifset use-ascii
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@example
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@group
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+--------------+-----------------------+
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| Data Type | Alignment Requirement |
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+--------------+-----------------------+
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| byte | 1 |
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| half-word | 2 |
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| word | 4 |
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| doubleword | 8 |
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+--------------+-----------------------+
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@end group
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@end example
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@end ifset
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@ifset use-tex
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@sp 1
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@tex
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\centerline{\vbox{\offinterlineskip\halign{
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\vrule\strut#&
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\hbox to 1.75in{\enskip\hfil#\hfil}&
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\vrule#&
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\hbox to 1.75in{\enskip\hfil#\hfil}&
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\vrule#\cr
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\noalign{\hrule}
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&\bf Data Type &&\bf Alignment Requirement&\cr\noalign{\hrule}
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&byte&&1&\cr\noalign{\hrule}
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&half-word&&2&\cr\noalign{\hrule}
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&word&&4&\cr\noalign{\hrule}
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&doubleword&&8&\cr\noalign{\hrule}
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}}\hfil}
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@end tex
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@end ifset
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@ifset use-html
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@html
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<CENTER>
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<TABLE COLS=2 WIDTH="60%" BORDER=2>
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<TR><TD ALIGN=center><STRONG>Data Type</STRONG></TD>
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<TD ALIGN=center><STRONG>Alignment Requirement</STRONG></TD></TR>
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<TR><TD ALIGN=center>byte</TD>
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<TD ALIGN=center>1</TD></TR>
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<TR><TD ALIGN=center>half-word</TD>
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<TD ALIGN=center>2</TD></TR>
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<TR><TD ALIGN=center>word</TD>
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<TD ALIGN=center>4</TD></TR>
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<TR><TD ALIGN=center>doubleword</TD>
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<TD ALIGN=center>8</TD></TR>
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</TABLE>
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</CENTER>
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@end html
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@end ifset
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Doubleword load and store operations are only available in
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PowerPC CPU models which are sixty-four bit implementations.
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RTEMS does not directly support any PowerPC Memory Management
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Units, therefore, virtual memory or segmentation systems
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involving the PowerPC are not supported.
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