forked from Imagelibrary/rtems
5d4a1edca0
- Defines CPU_Interrupt_frame in cpu_impl.h - Updates isq_asm.S to save/restore registers in matching order to interrupt frame
278 lines
7.6 KiB
ArmAsm
278 lines
7.6 KiB
ArmAsm
/*
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* This file contains the implementation of the function described in irq.h
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*/
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/*
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* Copyright (C) 1998 valette@crf.canon.fr
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*
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* COPYRIGHT (c) 1989-2011.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems/asm.h>
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#include <bspopts.h>
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#include <rtems/score/cpu.h>
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#include <rtems/score/percpu.h>
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#include <bsp.h> /* to establish dependency on prototype */
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#ifndef CPU_STACK_ALIGNMENT
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#error "Missing header? CPU_STACK_ALIGNMENT is not defined here"
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#endif
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/* Stack frame we use for intermediate storage */
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#define ARG_OFF 0
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#define EBX_OFF 4 /* ebx */
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#define EBP_OFF 8 /* code restoring ebp/esp relies on */
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#define ESP_OFF 12 /* esp being on top of ebp! */
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#ifdef __SSE__
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#ifdef RTEMS_SMP
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#error SMP with SSE support has not been tested. Use at your own risk.
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#endif
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/* need to be on 16 byte boundary for SSE, add 12 to do that */
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#define FRM_SIZ (20+12+512)
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#define SSE_OFF 32
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#else
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#define FRM_SIZ 16
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#endif
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BEGIN_CODE
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SYM (_ISR_Handler):
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/*
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* Before this was point is reached the vectors unique
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* entry point did the following:
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*
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* 1. saved scratch registers registers eax edx ecx"
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* 2. put the vector number in ecx.
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*
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* BEGINNING OF ESTABLISH SEGMENTS
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*
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* WARNING: If an interrupt can occur when the segments are
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* not correct, then this is where we should establish
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* the segments. In addition to establishing the
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* segments, it may be necessary to establish a stack
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* in the current data area on the outermost interrupt.
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*
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* NOTE: If the previous values of the segment registers are
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* pushed, do not forget to adjust SAVED_REGS.
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*
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* NOTE: Make sure the Lthread_dispatch_done code restores these
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* when this type of code is needed.
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*/
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/***** ESTABLISH SEGMENTS CODE GOES HERE ******/
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/*
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* END OF ESTABLISH SEGMENTS
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*/
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/*
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* Establish an aligned stack frame
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* original sp
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* saved ebp
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* saved ebx
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* vector arg to BSP_dispatch_isr <- aligned SP
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*/
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movl esp, eax
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subl $FRM_SIZ, esp
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movl eax, ESP_OFF(esp)
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movl ebp, EBP_OFF(esp)
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movl ebx, EBX_OFF(esp)
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/*
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* GCC versions starting with 4.3 no longer place the cld
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* instruction before string operations. We need to ensure
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* it is set correctly for ISR handlers.
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*/
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cld
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#ifdef __SSE__
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/* NOTE: SSE only is supported if the BSP enables fxsave/fxrstor
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* to save/restore SSE context! This is so far only implemented
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* for pc386!.
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*/
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/* We save SSE here (on the task stack) because we possibly
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* call other C-code (besides the ISR, namely _Thread_Dispatch())
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*/
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/* don't wait here; a possible exception condition will eventually be
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* detected when the task resumes control and executes a FP instruction
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fwait
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*/
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fxsave SSE_OFF(esp)
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fninit /* clean-slate FPU */
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movl $0x1f80, ARG_OFF(esp) /* use ARG_OFF as scratch space */
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ldmxcsr ARG_OFF(esp) /* clean-slate MXCSR */
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#endif
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/*
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* Now switch stacks if necessary
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*/
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PUBLIC (ISR_STOP)
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ISR_STOP:
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.check_stack_switch:
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movl esp, ebp /* ebp = previous stack pointer */
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andl $ - CPU_STACK_ALIGNMENT, esp /* Make sure esp is 16 byte aligned */
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GET_SELF_CPU_CONTROL ebx
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/* is this the outermost interrupt? */
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cmpl $0, PER_CPU_ISR_NEST_LEVEL(ebx)
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jne nested /* No, then continue */
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movl PER_CPU_INTERRUPT_STACK_HIGH(ebx), esp
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/*
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* We want to insure that the old stack pointer is in ebp
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* By saving it on every interrupt, all we have to do is
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* movl ebp->esp near the end of every interrupt.
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*/
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nested:
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incl PER_CPU_ISR_NEST_LEVEL(ebx) /* one nest level deeper */
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incl PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(ebx) /* disable
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multitasking */
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/*
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* ECX is preloaded with the vector number; store as arg
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* on top of stack. Note that _CPU_Interrupt_stack_high
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* was adjusted in _CPU_Interrupt_stack_setup() (score/rtems/cpu.h)
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* to make sure there is space.
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*/
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movl ecx, ARG_OFF(esp) /* store vector arg in stack */
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call BSP_dispatch_isr
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movl ARG_OFF(esp), ecx /* grab vector arg from stack */
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/*
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* Restore stack. This moves back to the task stack
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* when all interrupts are unnested.
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*/
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movl ebp, esp
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/*
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* Thread dispatching is necessary and allowed if and only if
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* dispatch_necessary == 1 and
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* isr_dispatch_disable == 0 and
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* thread_dispatch_disable_level == 0.
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*
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* Otherwise, continue with .Lthread_dispatch_done
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*/
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movl PER_CPU_DISPATCH_NEEDED(ebx), eax
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xorl PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(ebx), eax
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decl PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(ebx)
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orl PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(ebx), eax
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orl PER_CPU_ISR_DISPATCH_DISABLE(ebx), eax
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decl PER_CPU_ISR_NEST_LEVEL(ebx) /* one less ISR nest level */
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cmpl $0, eax
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jne .Lthread_dispatch_done /* Is task switch necessary? */
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.Ldo_thread_dispatch:
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/* Set ISR dispatch disable and thread dispatch disable level to one */
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movl $1, PER_CPU_ISR_DISPATCH_DISABLE(ebx)
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movl $1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(ebx)
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/* Call Thread_Do_dispatch(), this function will enable interrupts */
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push $EFLAGS_INTR_ENABLE /* Set interrupt flag manually */
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push ebx
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call _Thread_Do_dispatch
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/* Disable interrupts */
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cli
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addl $8, esp
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/* Sometimes after returning from _Thread_Do_dispatch current CPU and ebx ptr are different */
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GET_SELF_CPU_CONTROL ebx
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cmpb $0, PER_CPU_DISPATCH_NEEDED(ebx)
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jne .Ldo_thread_dispatch
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/* We are done with thread dispatching */
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movl $0, PER_CPU_ISR_DISPATCH_DISABLE(ebx)
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/*
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* fall through Lthread_dispatch_done to restore complete contex (scratch registers
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* eip, CS, Flags).
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*/
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.Lthread_dispatch_done:
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#ifdef __SSE__
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fwait
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fxrstor SSE_OFF(esp)
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#endif
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/* restore ebx, ebp and original esp */
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addl $EBX_OFF, esp
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popl ebx
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popl ebp
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popl esp
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/*
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* BEGINNING OF DE-ESTABLISH SEGMENTS
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*
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* NOTE: Make sure there is code here if code is added to
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* load the segment registers.
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*
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*/
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/******* DE-ESTABLISH SEGMENTS CODE GOES HERE ********/
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/*
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* END OF DE-ESTABLISH SEGMENTS
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*/
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popl edx
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popl ecx
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popl eax
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iret
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#define DISTINCT_INTERRUPT_ENTRY(_vector) \
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.p2align 4 ; \
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PUBLIC (rtems_irq_prologue_ ## _vector ) ; \
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SYM (rtems_irq_prologue_ ## _vector ): \
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pushl eax ; \
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pushl ecx ; \
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pushl edx ; \
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movl $ _vector, ecx ; \
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jmp SYM (_ISR_Handler) ;
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DISTINCT_INTERRUPT_ENTRY(0)
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DISTINCT_INTERRUPT_ENTRY(1)
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DISTINCT_INTERRUPT_ENTRY(2)
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DISTINCT_INTERRUPT_ENTRY(3)
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DISTINCT_INTERRUPT_ENTRY(4)
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DISTINCT_INTERRUPT_ENTRY(5)
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DISTINCT_INTERRUPT_ENTRY(6)
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DISTINCT_INTERRUPT_ENTRY(7)
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DISTINCT_INTERRUPT_ENTRY(8)
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DISTINCT_INTERRUPT_ENTRY(9)
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DISTINCT_INTERRUPT_ENTRY(10)
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DISTINCT_INTERRUPT_ENTRY(11)
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DISTINCT_INTERRUPT_ENTRY(12)
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DISTINCT_INTERRUPT_ENTRY(13)
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DISTINCT_INTERRUPT_ENTRY(14)
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DISTINCT_INTERRUPT_ENTRY(15)
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DISTINCT_INTERRUPT_ENTRY(16)
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/*
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* routine used to initialize the IDT by default
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*/
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PUBLIC (default_raw_idt_handler)
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PUBLIC (raw_idt_notify)
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SYM (default_raw_idt_handler):
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pusha
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cld
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mov esp, ebp
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andl $ - CPU_STACK_ALIGNMENT, esp
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call raw_idt_notify
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mov ebp, esp
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popa
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iret
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END_CODE
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END
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