forked from Imagelibrary/rtems
50539ba881
This support code is necessary for many Xilinx-provided bare metal device drivers supported on ARM, AArch64, and MicroBlaze platforms. Support for all of these architectures is kept under bsps/include due to multiple architecture variants being supported which requires complex logic in the build system. The imported files are and should be able to remain unmodified. Import information is kept in bsps/shared/xil/VERSION.
76 lines
2.0 KiB
C
76 lines
2.0 KiB
C
/******************************************************************************
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* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
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* SPDX-License-Identifier: MIT
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xil_cache.h
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*
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* @addtogroup a53_64_cache_apis Cortex A53 64bit Processor Cache Functions
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*
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* Cache functions provide access to cache related operations such as flush
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* and invalidate for instruction and data caches. It gives option to perform
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* the cache operations on a single cacheline, a range of memory and an entire
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* cache.
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*
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* @{
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 5.00 pkp 05/29/14 First release
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* </pre>
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*
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******************************************************************************/
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#ifndef XIL_CACHE_H
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#define XIL_CACHE_H
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#include "xil_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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*@cond nocomments
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*/
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/************************** Constant Definitions *****************************/
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#define L1_DATA_PREFETCH_CONTROL_MASK 0xE000
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#define L1_DATA_PREFETCH_CONTROL_SHIFT 13
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/**
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*@endcond
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*/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define Xil_DCacheFlushRange Xil_DCacheInvalidateRange
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/************************** Function Prototypes ******************************/
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void Xil_DCacheEnable(void);
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void Xil_DCacheDisable(void);
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void Xil_DCacheInvalidate(void);
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void Xil_DCacheInvalidateRange(INTPTR adr, INTPTR len);
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void Xil_DCacheInvalidateLine(INTPTR adr);
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void Xil_DCacheFlush(void);
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void Xil_DCacheFlushLine(INTPTR adr);
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void Xil_ICacheEnable(void);
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void Xil_ICacheDisable(void);
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void Xil_ICacheInvalidate(void);
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void Xil_ICacheInvalidateRange(INTPTR adr, INTPTR len);
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void Xil_ICacheInvalidateLine(INTPTR adr);
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void Xil_ConfigureL1Prefetch(u8 num);
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#ifdef __cplusplus
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}
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#endif
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#endif
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/**
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* @} End of "addtogroup a53_64_cache_apis".
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*/
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