forked from Imagelibrary/rtems
421 lines
10 KiB
C
421 lines
10 KiB
C
/*
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* This include file contains all private driver definitions for the
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* Zilog z85c30.
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*
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* COPYRIGHT (c) 1998 by Radstone Technology
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*
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*
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* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
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* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
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* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
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*
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* You are hereby granted permission to use, copy, modify, and distribute
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* this file, provided that this notice, plus the above copyright notice
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* and disclaimer, appears in all copies. Radstone Technology will provide
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* no support for this code.
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*
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* COPYRIGHT (c) 1989-1997.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may in
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* the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef __Z85C30_P_H
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#define __Z85C30_P_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Define Z85C30_STATIC to nothing while debugging so the entry points
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* will show up in the symbol table.
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*/
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#define Z85C30_STATIC
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/* #define Z85C30_STATIC static */
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/* bit values for write register 0 */
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/* command register */
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#define SCC_WR0_SEL_WR0 0x00
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#define SCC_WR0_SEL_WR1 0x01
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#define SCC_WR0_SEL_WR2 0x02
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#define SCC_WR0_SEL_WR3 0x03
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#define SCC_WR0_SEL_WR4 0x04
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#define SCC_WR0_SEL_WR5 0x05
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#define SCC_WR0_SEL_WR6 0x06
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#define SCC_WR0_SEL_WR7 0x07
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#define SCC_WR0_SEL_WR8 0x08
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#define SCC_WR0_SEL_WR9 0x09
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#define SCC_WR0_SEL_WR10 0x0a
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#define SCC_WR0_SEL_WR11 0x0b
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#define SCC_WR0_SEL_WR12 0x0c
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#define SCC_WR0_SEL_WR13 0x0d
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#define SCC_WR0_SEL_WR14 0x0e
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#define SCC_WR0_SEL_WR15 0x0f
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#define SCC_WR0_SEL_RD0 0x00
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#define SCC_WR0_SEL_RD1 0x01
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#define SCC_WR0_SEL_RD2 0x02
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#define SCC_WR0_SEL_RD3 0x03
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#define SCC_WR0_SEL_RD4 0x04
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#define SCC_WR0_SEL_RD5 0x05
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#define SCC_WR0_SEL_RD6 0x06
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#define SCC_WR0_SEL_RD7 0x07
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#define SCC_WR0_SEL_RD8 0x08
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#define SCC_WR0_SEL_RD9 0x09
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#define SCC_WR0_SEL_RD10 0x0a
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#define SCC_WR0_SEL_RD11 0x0b
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#define SCC_WR0_SEL_RD12 0x0c
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#define SCC_WR0_SEL_RD13 0x0d
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#define SCC_WR0_SEL_RD14 0x0e
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#define SCC_WR0_SEL_RD15 0x0f
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#define SCC_WR0_NULL_CODE 0x00
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#define SCC_WR0_RST_INT 0x10
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#define SCC_WR0_SEND_ABORT 0x18
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#define SCC_WR0_EN_INT_RX 0x20
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#define SCC_WR0_RST_TX_INT 0x28
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#define SCC_WR0_ERR_RST 0x30
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#define SCC_WR0_RST_HI_IUS 0x38
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#define SCC_WR0_RST_RX_CRC 0x40
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#define SCC_WR0_RST_TX_CRC 0x80
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#define SCC_WR0_RST_TX_UND 0xc0
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/* write register 2 */
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/* interrupt vector */
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/* bit values for write register 1 */
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/* tx/rx interrupt and data transfer mode definition */
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#define SCC_WR1_EXT_INT_EN 0x01
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#define SCC_WR1_TX_INT_EN 0x02
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#define SCC_WR1_PARITY 0x04
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#define SCC_WR1_RX_INT_DIS 0x00
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#define SCC_WR1_RX_INT_FIR 0x08
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#define SCC_WR1_INT_ALL_RX 0x10
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#define SCC_WR1_RX_INT_SPE 0x18
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#define SCC_WR1_RDMA_RECTR 0x20
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#define SCC_WR1_RDMA_FUNC 0x40
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#define SCC_WR1_RDMA_EN 0x80
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#define SCC_ENABLE_ALL_INTR \
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(SCC_WR1_EXT_INT_EN | SCC_WR1_TX_INT_EN | SCC_WR1_INT_ALL_RX)
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#define SCC_DISABLE_ALL_INTR 0x00
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#define SCC_ENABLE_ALL_INTR_EXCEPT_TX \
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(SCC_WR1_EXT_INT_EN | SCC_WR1_INT_ALL_RX)
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/* bit values for write register 3 */
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/* receive parameters and control */
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#define SCC_WR3_RX_EN 0x01
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#define SCC_WR3_SYNC_CHAR 0x02
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#define SCC_WR3_ADR_SEARCH 0x04
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#define SCC_WR3_RX_CRC_EN 0x08
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#define SCC_WR3_ENTER_HUNT 0x10
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#define SCC_WR3_AUTO_EN 0x20
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#define SCC_WR3_RX_5_BITS 0x00
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#define SCC_WR3_RX_7_BITS 0x40
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#define SCC_WR3_RX_6_BITS 0x80
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#define SCC_WR3_RX_8_BITS 0xc0
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/* bit values for write register 4 */
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/* tx/rx misc parameters and modes */
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#define SCC_WR4_PAR_EN 0x01
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#define SCC_WR4_PAR_EVEN 0x02
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#define SCC_WR4_SYNC_EN 0x00
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#define SCC_WR4_1_STOP 0x04
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#define SCC_WR4_2_STOP 0x0c
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#define SCC_WR4_8_SYNC 0x00
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#define SCC_WR4_16_SYNC 0x10
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#define SCC_WR4_SDLC 0x20
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#define SCC_WR4_EXT_SYNC 0x30
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#define SCC_WR4_1_CLOCK 0x00
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#define SCC_WR4_16_CLOCK 0x40
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#define SCC_WR4_32_CLOCK 0x80
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#define SCC_WR4_64_CLOCK 0xc0
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/* bit values for write register 5 */
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/* transmit parameter and controls */
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#define SCC_WR5_TX_CRC_EN 0x01
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#define SCC_WR5_RTS 0x02
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#define SCC_WR5_SDLC 0x04
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#define SCC_WR5_TX_EN 0x08
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#define SCC_WR5_SEND_BRK 0x10
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#define SCC_WR5_TX_5_BITS 0x00
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#define SCC_WR5_TX_7_BITS 0x20
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#define SCC_WR5_TX_6_BITS 0x40
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#define SCC_WR5_TX_8_BITS 0x60
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#define SCC_WR5_DTR 0x80
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/* write register 6 */
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/* sync chars or sdlc address field */
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/* write register 7 */
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/* sync char or sdlc flag */
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/* write register 8 */
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/* transmit buffer */
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/* bit values for write register 9 */
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/* master interrupt control */
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#define SCC_WR9_VIS 0x01
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#define SCC_WR9_NV 0x02
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#define SCC_WR9_DLC 0x04
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#define SCC_WR9_MIE 0x08
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#define SCC_WR9_STATUS_HI 0x10
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#define SCC_WR9_NO_RST 0x00
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#define SCC_WR9_CH_B_RST 0x40
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#define SCC_WR9_CH_A_RST 0x80
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#define SCC_WR9_HDWR_RST 0xc0
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/* bit values for write register 10 */
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/* misc tx/rx control bits */
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#define SCC_WR10_6_BIT_SYNC 0x01
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#define SCC_WR10_LOOP_MODE 0x02
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#define SCC_WR10_ABORT_UND 0x04
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#define SCC_WR10_MARK_IDLE 0x08
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#define SCC_WR10_ACT_POLL 0x10
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#define SCC_WR10_NRZ 0x00
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#define SCC_WR10_NRZI 0x20
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#define SCC_WR10_FM1 0x40
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#define SCC_WR10_FM0 0x60
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#define SCC_WR10_CRC_PRESET 0x80
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/* bit values for write register 11 */
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/* clock mode control */
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#define SCC_WR11_OUT_XTAL 0x00
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#define SCC_WR11_OUT_TX_CLK 0x01
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#define SCC_WR11_OUT_BR_GEN 0x02
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#define SCC_WR11_OUT_DPLL 0x03
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#define SCC_WR11_TRXC_OI 0x04
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#define SCC_WR11_TX_RTXC 0x00
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#define SCC_WR11_TX_TRXC 0x08
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#define SCC_WR11_TX_BR_GEN 0x10
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#define SCC_WR11_TX_DPLL 0x18
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#define SCC_WR11_RX_RTXC 0x00
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#define SCC_WR11_RX_TRXC 0x20
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#define SCC_WR11_RX_BR_GEN 0x40
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#define SCC_WR11_RX_DPLL 0x60
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#define SCC_WR11_RTXC_XTAL 0x80
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/* write register 12 */
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/* lower byte of baud rate generator time constant */
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/* write register 13 */
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/* upper byte of baud rate generator time constant */
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/* bit values for write register 14 */
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/* misc control bits */
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#define SCC_WR14_BR_EN 0x01
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#define SCC_WR14_BR_SRC 0x02
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#define SCC_WR14_DTR_FUNC 0x04
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#define SCC_WR14_AUTO_ECHO 0x08
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#define SCC_WR14_LCL_LOOP 0x10
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#define SCC_WR14_NULL 0x00
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#define SCC_WR14_SEARCH 0x20
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#define SCC_WR14_RST_CLK 0x40
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#define SCC_WR14_DIS_DPLL 0x60
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#define SCC_WR14_SRC_BR 0x80
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#define SCC_WR14_SRC_RTXC 0xa0
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#define SCC_WR14_FM_MODE 0xc0
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#define SCC_WR14_NRZI 0xe0
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/* bit values for write register 15 */
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/* external/status interrupt control */
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#define SCC_WR15_ZERO_CNT 0x02
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#define SCC_WR15_CD_IE 0x08
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#define SCC_WR15_SYNC_IE 0x10
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#define SCC_WR15_CTS_IE 0x20
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#define SCC_WR15_TX_UND_IE 0x40
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#define SCC_WR15_BREAK_IE 0x80
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/* bit values for read register 0 */
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/* tx/rx buffer status and external status */
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#define SCC_RR0_RX_AVAIL 0x01
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#define SCC_RR0_ZERO_CNT 0x02
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#define SCC_RR0_TX_EMPTY 0x04
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#define SCC_RR0_CD 0x08
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#define SCC_RR0_SYNC 0x10
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#define SCC_RR0_CTS 0x20
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#define SCC_RR0_TX_UND 0x40
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#define SCC_RR0_BREAK 0x80
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/* bit values for read register 1 */
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#define SCC_RR1_ALL_SENT 0x01
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#define SCC_RR1_RES_CD_2 0x02
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#define SCC_RR1_RES_CD_1 0x01
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#define SCC_RR1_RES_CD_0 0x08
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#define SCC_RR1_PAR_ERR 0x10
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#define SCC_RR1_RX_OV_ERR 0x20
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#define SCC_RR1_CRC_ERR 0x40
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#define SCC_RR1_END_FRAME 0x80
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/* read register 2 */
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/* interrupt vector */
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/* bit values for read register 3 */
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/* interrupt pending register */
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#define SCC_RR3_B_EXT_IP 0x01
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#define SCC_RR3_B_TX_IP 0x02
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#define SCC_RR3_B_RX_IP 0x04
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#define SCC_RR3_A_EXT_IP 0x08
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#define SCC_RR3_A_TX_IP 0x10
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#define SCC_RR3_A_RX_IP 0x20
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/* read register 8 */
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/* receive data register */
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/* bit values for read register 10 */
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/* misc status bits */
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#define SCC_RR10_ON_LOOP 0x02
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#define SCC_RR10_LOOP_SEND 0x10
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#define SCC_RR10_2_CLK_MIS 0x40
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#define SCC_RR10_1_CLK_MIS 0x80
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/* read register 12 */
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/* lower byte of time constant */
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/* read register 13 */
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/* upper byte of time constant */
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/* bit values for read register 15 */
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/* external/status ie bits */
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#define SCC_RR15_ZERO_CNT 0x02
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#define SCC_RR15_CD_IE 0x08
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#define SCC_RR15_SYNC_IE 0x10
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#define SCC_RR15_CTS_IE 0x20
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#define SCC_RR15_TX_UND_IE 0x40
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#define SCC_RR15_BREAK_IE 0x80
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typedef struct _z85c30_context
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{
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uint8_t ucModemCtrl;
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} z85c30_context;
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/*
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* The following macro calculates the Baud constant. For the Z85C30 chip.
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*
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* Note: baud constant = ((clock frequency / Clock_X) / (2 * Baud Rate)) - 2
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* eg ((10,000,000 / 16) / (2 * Baud Rate)) - 2
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*/
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#define Z85C30_Baud( _clock, _baud_rate ) \
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( ((_clock) /( 16 * 2 * _baud_rate)) - 2)
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#define Z85C30_Status_Is_RX_character_available(_status) \
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((_status) & SCC_RR0_RX_AVAIL)
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#define Z85C30_Status_Is_TX_buffer_empty(_status) \
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((_status) & SCC_RR0_TX_EMPTY)
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#define Z85C30_Status_Is_CTS_asserted(_status) \
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((_status) & SCC_RR0_CTS)
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#define Z85C30_Status_Is_break_abort(_status) \
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((_status) & SCC_RR0_BREAK)
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/*
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* Private routines
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*/
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Z85C30_STATIC void z85c30_initialize_port(
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int minor
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);
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Z85C30_STATIC void z85c30_init(int minor);
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Z85C30_STATIC int z85c30_set_attributes(
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int minor,
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const struct termios *t
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);
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Z85C30_STATIC int z85c30_open(
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int major,
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int minor,
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void * arg
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);
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Z85C30_STATIC int z85c30_close(
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int major,
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int minor,
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void * arg
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);
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Z85C30_STATIC void z85c30_write_polled(
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int minor,
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char cChar
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);
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Z85C30_STATIC int z85c30_assert_RTS(
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int minor
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);
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Z85C30_STATIC int z85c30_negate_RTS(
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int minor
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);
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Z85C30_STATIC int z85c30_assert_DTR(
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int minor
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);
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Z85C30_STATIC int z85c30_negate_DTR(
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int minor
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);
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Z85C30_STATIC void z85c30_initialize_interrupts(int minor);
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Z85C30_STATIC ssize_t z85c30_write_support_int(
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int minor,
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const char *buf,
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size_t len
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);
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Z85C30_STATIC ssize_t z85c30_write_support_polled(
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int minor,
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const char *buf,
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size_t len
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);
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Z85C30_STATIC int z85c30_inbyte_nonblocking_polled(
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int minor
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);
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Z85C30_STATIC void z85c30_enable_interrupts(
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int minor,
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int interrupt_mask
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);
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Z85C30_STATIC void z85c30_process(
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int minor,
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uint8_t ucIntPend
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);
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Z85C30_STATIC rtems_isr z85c30_isr(
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rtems_vector_number vector
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);
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#ifdef __cplusplus
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}
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#endif
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#endif
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