forked from Imagelibrary/rtems
135 lines
2.9 KiB
C
135 lines
2.9 KiB
C
/*
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* Copyright (c) 2013, 2018 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <info@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#define ARM_CP15_TEXT_SECTION BSP_START_TEXT_SECTION
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#include <bsp.h>
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#include <bsp/bootcard.h>
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#include <bsp/fdt.h>
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#include <bsp/linker-symbols.h>
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#include <bsp/start.h>
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#include <bsp/arm-cp15-start.h>
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#include <bsp/arm-a9mpcore-start.h>
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#include <rtems/sysinit.h>
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#include <libfdt.h>
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BSP_START_DATA_SECTION static arm_cp15_start_section_config
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imx_mmu_config_table[] = {
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ARMV7_CP15_START_DEFAULT_SECTIONS,
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{
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.begin = 0x00a00000U,
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.end = 0x70000000U,
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.flags = ARMV7_MMU_DEVICE
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}
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};
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BSP_START_DATA_SECTION static char memory_path[] = "/memory";
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BSP_START_TEXT_SECTION static void setup_mmu_and_cache(void)
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{
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const void *fdt;
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int node;
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uint32_t ctrl;
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fdt = bsp_fdt_get();
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node = fdt_path_offset_namelen(
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fdt,
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memory_path,
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(int) sizeof(memory_path) - 1
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);
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if (node >= 0) {
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int len;
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const void *val;
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val = fdt_getprop(fdt, node, "reg", &len);
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if (len == 8) {
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uint32_t begin;
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uint32_t size;
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begin = fdt32_to_cpu(((fdt32_t *) val)[0]);
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size = fdt32_to_cpu(((fdt32_t *) val)[1]);
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/* The heap code does not like an end address of zero */
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if (begin + size == 0) {
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size -= 4;
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}
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imx_mmu_config_table[ARMV7_CP15_START_WORKSPACE_ENTRY_INDEX].end =
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begin + size;
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}
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}
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ctrl = arm_cp15_start_setup_mmu_and_cache(
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ARM_CP15_CTRL_A,
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ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
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);
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arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache(
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ctrl,
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(uint32_t *) bsp_translation_table_base,
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ARM_MMU_DEFAULT_CLIENT_DOMAIN,
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&imx_mmu_config_table[0],
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RTEMS_ARRAY_SIZE(imx_mmu_config_table)
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);
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}
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BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
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{
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#ifdef RTEMS_SMP
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uint32_t cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id();
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arm_a9mpcore_start_enable_smp_in_auxiliary_control();
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if (cpu_id != 0) {
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arm_a9mpcore_start_on_secondary_processor();
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}
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#endif
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}
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BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
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{
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arm_a9mpcore_start_set_vector_base();
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bsp_start_copy_sections();
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setup_mmu_and_cache();
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bsp_start_clear_bss();
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}
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static Memory_Area _Memory_Areas[1];
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static void bsp_memory_initialize(void)
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{
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_Memory_Initialize(
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&_Memory_Areas[0],
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imx_mmu_config_table[ARMV7_CP15_START_WORKSPACE_ENTRY_INDEX].begin,
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imx_mmu_config_table[ARMV7_CP15_START_WORKSPACE_ENTRY_INDEX].end
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);
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}
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RTEMS_SYSINIT_ITEM(
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bsp_memory_initialize,
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RTEMS_SYSINIT_MEMORY,
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RTEMS_SYSINIT_ORDER_MIDDLE
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);
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static const Memory_Information _Memory_Information =
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MEMORY_INFORMATION_INITIALIZER(_Memory_Areas);
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const Memory_Information *_Memory_Get(void)
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{
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return &_Memory_Information;
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}
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