forked from Imagelibrary/rtems
9964895866
Adjust build support files to new directory layout. This patch is a part of the BSP source reorganization. Update #3285.
36 lines
1.6 KiB
C
36 lines
1.6 KiB
C
/*
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* CSB336 Memory Map
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*
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* Copyright (c) 2004 by Cogent Computer Systems
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* Written by Jay Monkman <jtm@lopingdog.com>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems.h>
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#include <libcpu/mmu.h>
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/* Remember, the ARM920 has 64 TLBs. If you have more 1MB sections than
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* that, you'll have TLB lookups, which could hurt performance.
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*/
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mmu_sect_map_t mem_map[] = {
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/* <phys addr> <virt addr> <size> <flags> */
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{0x08200000, 0x00000000, 1, MMU_CACHE_WBACK}, /* Mirror of SDRAM */
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{0x00100000, 0x00100000, 1, MMU_CACHE_NONE}, /* Bootstrap ROM */
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{0x00200000, 0x00200000, 2, MMU_CACHE_NONE}, /* Internal Regs + eSRAM */
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{0x08000000, 0x08000000, 1, MMU_CACHE_NONE}, /* SDRAM */
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{0x08100000, 0x08100000, 1, MMU_CACHE_WTHROUGH}, /* SDRAM */
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{0x08200000, 0x08200000, 30, MMU_CACHE_WBACK}, /* SDRAM */
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{0x10000000, 0x10000000, 8, MMU_CACHE_NONE}, /* CS0 - Flash */
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{0x12000000, 0x12000000, 1, MMU_CACHE_NONE}, /* CS1 - enet */
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{0x13000000, 0x13000000, 1, MMU_CACHE_NONE}, /* CS2 - */
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{0x14000000, 0x14000000, 1, MMU_CACHE_NONE}, /* CS3 - */
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{0x15000000, 0x15000000, 1, MMU_CACHE_NONE}, /* CS4 - */
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{0x16000000, 0x16000000, 1, MMU_CACHE_NONE}, /* CS5 - */
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{0x50000000, 0x50000000, 1, MMU_CACHE_NONE}, /* ARM Test Regs */
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{0x00000000, 0x00000000, 0, 0} /* The end */
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};
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