forked from Imagelibrary/rtems
5d5b9eeb08
This patch changes the license to BSD-2 for all source files where the copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research. Some files also includes copyright right statements from OAR and/or embedded Brains in addition to Gaisler. Updates #3053.
1478 lines
35 KiB
C
1478 lines
35 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* GRIOMMU Driver Interface
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*
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* COPYRIGHT (c) 2017
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* Cobham Gaisler AB
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdlib.h>
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#include <string.h>
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#include <drvmgr/drvmgr.h>
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#include <grlib/ambapp_bus.h>
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#include <grlib/ambapp.h>
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#include <rtems.h>
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#include <rtems/bspIo.h>
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#include <bsp.h>
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#include <grlib/griommu.h>
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#include <grlib/grlib_impl.h>
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/*#define STATIC*/
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#define STATIC static
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/*#define INLINE*/
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#define INLINE inline
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#define UNUSED __attribute__((unused))
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/*#define DEBUG 1*/
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#ifdef DEBUG
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#define DBG(x...) printf(x)
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#else
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#define DBG(x...)
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#endif
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/*
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* GRIOMMU CAP0 register fields
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*/
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#define CAP0_A (0x1 << CAP0_A_BIT)
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#define CAP0_AC (0x1 << CAP0_AC_BIT)
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#define CAP0_CA (0x1 << CAP0_CA_BIT)
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#define CAP0_CP (0x1 << CAP0_CP_BIT)
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#define CAP0_NARB (0xf << CAP0_NARB_BIT)
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#define CAP0_CS (0x1 << CAP0_CS_BIT)
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#define CAP0_FT (0x3 << CAP0_FT_BIT)
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#define CAP0_ST (0x1 << CAP0_ST_BIT)
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#define CAP0_I (0x1 << CAP0_I_BIT)
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#define CAP0_IT (0x1 << CAP0_IT_BIT)
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#define CAP0_IA (0x1 << CAP0_IA_BIT)
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#define CAP0_IP (0x1 << CAP0_IP_BIT)
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#define CAP0_MB (0x1 << CAP0_MB_BIT)
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#define CAP0_GRPS (0xf << CAP0_GRPS_BIT)
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#define CAP0_MSTS (0xf << CAP0_MSTS_BIT)
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#define CAP0_A_BIT 31
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#define CAP0_AC_BIT 30
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#define CAP0_CA_BIT 29
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#define CAP0_CP_BIT 28
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#define CAP0_NARB_BIT 20
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#define CAP0_CS_BIT 19
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#define CAP0_FT_BIT 17
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#define CAP0_ST_BIT 16
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#define CAP0_I_BIT 15
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#define CAP0_IT_BIT 14
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#define CAP0_IA_BIT 13
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#define CAP0_IP_BIT 12
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#define CAP0_MB_BIT 8
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#define CAP0_GRPS_BIT 4
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#define CAP0_MSTS_BIT 0
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/*
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* GRIOMMU CAP1 register fields
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*/
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#define CAP1_CADDR (0xfff << CAP1_CADDR_BIT)
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#define CAP1_CMASK (0xf << CAP1_CMASK_BIT)
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#define CAP1_CTAGBITS (0xff << CAP1_CTAGBITS_BIT)
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#define CAP1_CISIZE (0x7 << CAP1_CISIZE_BIT)
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#define CAP1_CLINES (0x1f << CAP1_CLINES_BIT)
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#define CAP1_CADDR_BIT 20
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#define CAP1_CMASK_BIT 16
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#define CAP1_CTAGBITS_BIT 8
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#define CAP1_CISIZE_BIT 5
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#define CAP1_CLINES_BIT 0
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/*
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* GRIOMMU CTRL register fields
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* DEFINED IN HEADER FILE
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*/
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/*
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* GRIOMMU FLUSH register fields
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*/
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#define FLUSH_FGRP (0xf << FLUSH_FGRP_BIT)
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#define FLUSH_GF (0x1 << FLUSH_GF_BIT)
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#define FLUSH_F (0x1 << FLUSH_F_BIT)
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#define FLUSH_FGRP_BIT 4
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#define FLUSH_GF_BIT 1
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#define FLUSH_F_BIT 0
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/*
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* GRIOMMU STATUS register fields
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*/
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#define STS_PE (0x1 << STS_PE_BIT)
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#define STS_DE (0x1 << STS_DE_BIT)
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#define STS_FC (0x1 << STS_FC_BIT)
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#define STS_FL (0x1 << STS_FL_BIT)
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#define STS_AD (0x1 << STS_AD_BIT)
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#define STS_TE (0x1 << STS_TE_BIT)
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#define STS_ALL (STS_PE | STS_DE | STS_FC | STS_FL | STS_AD | STS_TE)
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#define STS_PE_BIT 5
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#define STS_DE_BIT 4
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#define STS_FC_BIT 3
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#define STS_FL_BIT 2
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#define STS_AD_BIT 1
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#define STS_TE_BIT 0
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/*
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* GRIOMMU IMASK register fields
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*/
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#define IMASK_PEI (0x1 << IMASK_PEI_BIT)
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#define IMASK_FCI (0x1 << IMASK_FCI_BIT)
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#define IMASK_FLI (0x1 << IMASK_FLI_BIT)
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#define IMASK_ADI (0x1 << IMASK_ADI_BIT)
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#define IMASK_TEI (0x1 << IMASK_TEI_BIT)
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#define IMASK_ALL (IMASK_PEI | IMASK_FCI | IMASK_FLI | IMASK_ADI | IMASK_TEI)
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#define IMASK_PEI_BIT 5
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#define IMASK_FCI_BIT 3
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#define IMASK_FLI_BIT 2
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#define IMASK_ADI_BIT 1
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#define IMASK_TEI_BIT 0
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/*
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* GRIOMMU MASTER register fields
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*/
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/* DEFINED IN HEADER FILE
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#define MASTER_VENDOR (0xff << MASTER_VENDOR_BIT)
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#define MASTER_DEVICE (0xfff << MASTER_DEVICE_BIT)
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#define MASTER_BS (0x1 << MASTER_BS_BIT)
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#define MASTER_GROUP (0xf << MASTER_GROUP_BIT)
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#define MASTER_VENDOR_BIT 24
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#define MASTER_DEVICE_BIT 12
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#define MASTER_BS_BIT 4
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#define MASTER_GROUP_BIT 0
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*/
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#define MASTER_BS_BUS0 0
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#define MASTER_BS_BUS1 MASTER_BS
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/*
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* GRIOMMU GROUP register fields
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*/
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#define GRP_BASE (0xfffffff << GRP_BASE_BIT)
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#define GRP_P (0x1 << GRP_P_BIT)
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#define GRP_AG (0x1 << GRP_AG_BIT)
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#define GRP_BASE_BIT 4
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#define GRP_P_BIT 1
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#define GRP_AG_BIT 0
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#define REG_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (unsigned int)(val))
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#define REG_READ(addr) (*(volatile unsigned int *)(addr))
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/*
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* GRIOMMU APB Register MAP
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*/
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struct griommu_regs {
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volatile unsigned int cap0; /* 0x00 - Capability 0 */
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volatile unsigned int cap1; /* 0x04 - Capability 1 */
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volatile unsigned int cap2; /* 0x08 - Capability 2 */
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volatile unsigned int resv1; /* 0x0c - Reserved */
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volatile unsigned int ctrl; /* 0x10 - Control */
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volatile unsigned int flush; /* 0x14 - TLB/cache flush */
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volatile unsigned int status; /* 0x18 - Status */
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volatile unsigned int imask; /* 0x1c - Interrupt mask */
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volatile unsigned int ahbstat; /* 0x20 - AHB Failing Access */
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volatile unsigned int resv2[7]; /* 0x24-0x3c - Reserved. No access */
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volatile unsigned int master[16]; /* 0x40-0x7c - Master configuration */
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volatile unsigned int grp_ctrl[16]; /* 0x80-0xbc - Group control */
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volatile unsigned int diag_ca; /* 0xc0 - Diagnostic cache access */
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volatile unsigned int diag_cad[8]; /* 0xc4-0xe0 - Diagnostic cache data */
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volatile unsigned int diag_cat; /* 0xe4 - Diagnostic cache tag */
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volatile unsigned int ei_data; /* 0xe8 - Data RAM error injection */
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volatile unsigned int ei_tag; /* 0xec - Tag RAM error injection */
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volatile unsigned int resv3[4]; /* 0xf0-0xfc - Reserved. No access */
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volatile unsigned int asmpctrl[16]; /* 0x100-0x13c - ASMP access control */
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};
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#define DEVNAME_LEN 9
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/*
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* GRIOMMU Driver private data struture
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*/
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struct griommu_priv {
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struct drvmgr_dev *dev;
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char devname[DEVNAME_LEN];
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/* GRIOMMU control registers */
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struct griommu_regs *regs;
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/* GRIOMMU capabilities */
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int apv;
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int apv_cache;
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int apv_cache_addr;
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int conf_pagesize;
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int groups;
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int masters;
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/* GRIOMMU page size */
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int pagesize;
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/* GRIOMMU APV cache */
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int cache_enabled;
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int group_addressing;
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/* User defined ISR */
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griommu_isr_t isr;
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void *isr_arg;
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};
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/*
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* GRIOMMU internal prototypes
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*/
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/* -Register access functions */
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STATIC INLINE unsigned int griommu_reg_cap0(void);
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STATIC INLINE unsigned int griommu_reg_cap1(void);
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STATIC INLINE unsigned int griommu_reg_ctrl(void);
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STATIC INLINE int griommu_reg_ctrl_set(unsigned int val);
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STATIC INLINE int griommu_reg_flush_set(unsigned int val);
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STATIC INLINE unsigned int griommu_reg_status(void);
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STATIC INLINE int griommu_reg_status_clear(unsigned int val);
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STATIC INLINE unsigned int griommu_reg_imask(void);
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STATIC INLINE int griommu_reg_imask_set(int mask);
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STATIC INLINE unsigned int griommu_reg_ahbfas(void);
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STATIC INLINE unsigned int griommu_reg_master(int master);
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STATIC INLINE int griommu_reg_master_set(int master, unsigned int val);
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STATIC INLINE unsigned int griommu_reg_group(int group);
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STATIC INLINE int griommu_reg_group_set(int group, unsigned int val);
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/* APV helper functions */
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STATIC void griommu_apv_set_word(unsigned int * wordptr, int startbitidx,
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int nbits, unsigned int val);
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STATIC int griommu_apv_set(void * apv, int index, int size, unsigned int val);
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/* -Init function called by drvmgr */
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int griommu_init1(struct drvmgr_dev *dev);
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STATIC int griommu_init(struct griommu_priv *priv);
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/* -IRQ handler */
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void griommu_isr(void *arg);
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/*
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* GRIOMMU static members
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*/
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static struct griommu_priv *griommupriv = NULL;
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/* GRIOMMU DRIVER */
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struct drvmgr_drv_ops griommu_ops =
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{
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.init = {griommu_init1, NULL, NULL, NULL},
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.remove = NULL,
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.info = NULL
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};
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struct amba_dev_id griommu_ids[] =
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{
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{VENDOR_GAISLER, GAISLER_GRIOMMU},
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{0, 0} /* Mark end of table */
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};
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struct amba_drv_info griommu_info =
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{
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{
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DRVMGR_OBJ_DRV, /* Driver */
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NULL, /* Next driver */
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NULL, /* Device list */
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DRIVER_AMBAPP_GAISLER_GRIOMMU_ID,/* Driver ID */
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"GRIOMMU_DRV", /* Driver Name */
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DRVMGR_BUS_TYPE_AMBAPP, /* Bus Type */
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&griommu_ops,
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NULL, /* Funcs */
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0, /* No devices yet */
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sizeof(struct griommu_priv), /* Make drvmgr alloc private */
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},
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&griommu_ids[0]
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};
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void griommu_register_drv(void)
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{
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DBG("Registering GRIOMMU driver\n");
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drvmgr_drv_register(&griommu_info.general);
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}
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/* Initializes the GRIOMMU core and driver
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*
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* Return values
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* 0 Successful initalization
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*/
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STATIC int griommu_init(struct griommu_priv *priv)
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{
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struct ambapp_ahb_info *ahb;
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struct amba_dev_info *ainfo = priv->dev->businfo;
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/* Find GRIOMMU core from Plug&Play information */
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ahb = ainfo->info.ahb_slv;
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/* Found GRIOMMU core, init private structure */
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priv->regs = (struct griommu_regs *)ahb->start[0];
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/* Mask all interrupts */
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griommu_reg_imask_set(0);
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/* Initialize GRIOMMU capabilities */
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uint32_t cap0 = griommu_reg_cap0();
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priv->apv = (cap0 & CAP0_A) >> CAP0_A_BIT;
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priv->apv_cache = (cap0 & CAP0_AC) >> CAP0_AC_BIT;
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priv->apv_cache_addr = (cap0 & CAP0_CA) >> CAP0_CA_BIT;
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priv->conf_pagesize = (cap0 & CAP0_CS) >> CAP0_CS_BIT;
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priv->groups = ((cap0 & CAP0_GRPS) >> CAP0_GRPS_BIT) + 1;
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priv->masters = ((cap0 & CAP0_MSTS) >> CAP0_MSTS_BIT) + 1;
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/* Get GRIOMMU pagesize */
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uint32_t ctrl = griommu_reg_ctrl();
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if (priv->conf_pagesize){
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priv->pagesize = (4*1024 << ((ctrl & CTRL_PGSZ) >> CTRL_PGSZ_BIT));
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}else{
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priv->pagesize = 4*1024;
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}
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priv->cache_enabled = (ctrl & CTRL_CE);
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priv->group_addressing = (ctrl & CTRL_GS);
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DBG("GRIOMMU Capabilities: APV=%d, APVC=%d, APVCA=%d, CS=%d, "
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"GRPS=%d, MSTS=%d\n",
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priv->apv, priv->apv_cache, priv->apv_cache_addr,
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priv->conf_pagesize, priv->groups, priv->masters);
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DBG("GRIOMMU driver initialized\n");
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return 0;
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}
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/* Called when a core is found with the AMBA device and vendor ID
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* given in griommu_ids[]. IRQ, Console does not work here
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*/
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int griommu_init1(struct drvmgr_dev *dev)
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{
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int status;
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struct griommu_priv *priv;
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DBG("GRIOMMU[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name);
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if (griommupriv) {
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DBG("Driver only supports one GRIOMMU core\n");
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return DRVMGR_FAIL;
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}
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priv = dev->priv;
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if (!priv)
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return DRVMGR_NOMEM;
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priv->dev = dev;
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strncpy(&priv->devname[0], "griommu0", DEVNAME_LEN);
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griommupriv = priv;
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/* Initialize GRIOMMU Hardware */
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status = griommu_init(priv);
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if (status) {
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printk("Failed to initialize griommu driver %d\n", status);
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return -1;
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}
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return DRVMGR_OK;
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}
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STATIC INLINE unsigned int griommu_reg_cap0(void)
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{
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struct griommu_priv *priv = griommupriv;
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return REG_READ(&priv->regs->cap0);
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}
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STATIC INLINE unsigned int griommu_reg_cap1(void)
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{
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struct griommu_priv *priv = griommupriv;
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return REG_READ(&priv->regs->cap1);
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}
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STATIC INLINE unsigned int griommu_reg_ctrl(void)
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{
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struct griommu_priv *priv = griommupriv;
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return REG_READ(&priv->regs->ctrl);
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}
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STATIC INLINE int griommu_reg_ctrl_set(unsigned int val)
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{
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struct griommu_priv *priv = griommupriv;
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REG_WRITE(&priv->regs->ctrl, val);
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return 0;
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}
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STATIC INLINE int griommu_reg_flush_set(unsigned int val)
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{
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struct griommu_priv *priv = griommupriv;
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REG_WRITE(&priv->regs->flush, val);
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return 0;
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}
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STATIC INLINE unsigned int griommu_reg_status(void)
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{
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struct griommu_priv *priv = griommupriv;
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return REG_READ(&priv->regs->status);
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}
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STATIC INLINE int griommu_reg_status_clear(unsigned int val)
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{
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struct griommu_priv *priv = griommupriv;
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/* Clear errors */
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REG_WRITE(&priv->regs->status, (val & STS_ALL));
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return 0;
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}
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STATIC INLINE unsigned int griommu_reg_imask(void)
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{
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struct griommu_priv *priv = griommupriv;
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return REG_READ(&priv->regs->imask);
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}
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STATIC INLINE int griommu_reg_imask_set(int mask)
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{
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struct griommu_priv *priv = griommupriv;
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/* Clear errors */
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REG_WRITE(&priv->regs->imask, (mask & IMASK_ALL));
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return 0;
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}
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STATIC INLINE unsigned int griommu_reg_ahbfas(void)
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{
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struct griommu_priv *priv = griommupriv;
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return REG_READ(&priv->regs->ahbstat);
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}
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STATIC INLINE int griommu_reg_master_set(int master, unsigned int val)
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{
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struct griommu_priv *priv = griommupriv;
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/* Change master conf */
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REG_WRITE(&priv->regs->master[master], val);
|
|
return 0;
|
|
}
|
|
|
|
STATIC INLINE unsigned int griommu_reg_master(int master)
|
|
{
|
|
struct griommu_priv *priv = griommupriv;
|
|
|
|
return REG_READ(&priv->regs->master[master]);
|
|
}
|
|
|
|
STATIC INLINE unsigned int griommu_reg_group(int group)
|
|
{
|
|
struct griommu_priv *priv = griommupriv;
|
|
|
|
return REG_READ(&priv->regs->grp_ctrl[group]);
|
|
}
|
|
|
|
STATIC INLINE int griommu_reg_group_set(int group, unsigned int val)
|
|
{
|
|
struct griommu_priv *priv = griommupriv;
|
|
|
|
REG_WRITE(&priv->regs->grp_ctrl[group], val);
|
|
return 0;
|
|
}
|
|
|
|
STATIC void griommu_apv_set_word(unsigned int * wordptr, int startbitidx,
|
|
int nbits, unsigned int val)
|
|
{
|
|
unsigned int mask;
|
|
unsigned int word = *wordptr;
|
|
int endbitidx = startbitidx + nbits - 1;
|
|
|
|
/* Set initial mask */
|
|
mask = 0xffffffff;
|
|
|
|
/* Adjust mask for the starting bit */
|
|
mask >>= startbitidx;
|
|
|
|
/* Adjust mask for the end bit */
|
|
mask >>= (31 - endbitidx);
|
|
mask <<= (31 - endbitidx);
|
|
|
|
DBG("Setting word: startbitdx=%d, endbitidx=%d, mask=0x%02x",
|
|
startbitidx, endbitidx, (unsigned int) mask);
|
|
|
|
/* Clear written bits with mask */
|
|
word &= ~(mask);
|
|
|
|
/* Set bits in val with mask */
|
|
mask &= val;
|
|
word |= mask;
|
|
|
|
DBG(", old word=0x%08x, new word=0x%08x\n",*wordptr, word);
|
|
|
|
/* Write word */
|
|
*wordptr=word;
|
|
}
|
|
|
|
/* Set certains bits of the APV to val */
|
|
STATIC int griommu_apv_set(void * apv, int index, int size, unsigned int val)
|
|
{
|
|
unsigned int * words = (unsigned int *) apv;
|
|
int len = size;
|
|
int wordidx = (index/32);
|
|
int startbit = (index % 32);
|
|
int nbits;
|
|
int nwords;
|
|
|
|
/* First incomplete word is a special case */
|
|
if (startbit != 0){
|
|
/* Get how many bits are we changing in this word */
|
|
if (startbit + len < 32){
|
|
nbits = len;
|
|
}else{
|
|
nbits = 32 - startbit;
|
|
}
|
|
griommu_apv_set_word(&words[wordidx], startbit, nbits, val);
|
|
DBG("First word: wordidx=%d, startbit=%d, bits=%d, val=0x%08x\n",
|
|
wordidx, startbit, nbits, words[wordidx]);
|
|
|
|
/* Update wordidx and len */
|
|
len = len - nbits;
|
|
wordidx++;
|
|
}
|
|
|
|
/* Write all complete full words */
|
|
if (len != 0){
|
|
nwords = (len/32);
|
|
memset((void *) &words[wordidx], val, nwords*4);
|
|
DBG("Middle words: wordidx=%d, nwords=%d\n", wordidx, nwords);
|
|
/* Update wordidx and len*/
|
|
wordidx = wordidx + nwords;
|
|
len = len - nwords*32;
|
|
}
|
|
|
|
/* Last word is a special case */
|
|
if (len != 0){
|
|
nbits = len;
|
|
griommu_apv_set_word(&words[wordidx], 0, nbits, val);
|
|
DBG("First word: wordidx=%d, startbit=%d, bits=%d, val=0x%08x\n",
|
|
wordidx, 0, nbits, words[wordidx]);
|
|
/* Update len */
|
|
len = len - (nbits);
|
|
}
|
|
|
|
return GRIOMMU_ERR_OK;
|
|
}
|
|
|
|
/* GRIOMMU Interrupt handler, called when there may be a GRIOMMU interrupt.
|
|
*/
|
|
void griommu_isr(void *arg)
|
|
{
|
|
struct griommu_priv *priv = arg;
|
|
unsigned int sts = griommu_reg_status();
|
|
unsigned int mask = griommu_reg_imask();
|
|
unsigned int access = griommu_reg_ahbfas();
|
|
|
|
/* Make sure that the interrupt is pending and unmasked,
|
|
* otherwise it migth have been other core
|
|
* sharing the same interrupt line */
|
|
if ((sts & STS_ALL) & (mask & IMASK_ALL)){
|
|
/* Reset error status */
|
|
griommu_reg_status_clear(sts);
|
|
/* Execute user IRQ (ther will always be one ISR */
|
|
(priv->isr)(priv->isr_arg, access, sts);
|
|
}
|
|
}
|
|
|
|
/* Setup IOMMU master:
|
|
*/
|
|
int griommu_master_setup(int master, int group, int options)
|
|
{
|
|
struct griommu_priv * priv = griommupriv;
|
|
|
|
if (priv == NULL){
|
|
DBG("GRIOMMU not initialized.\n");
|
|
return GRIOMMU_ERR_NOINIT;
|
|
}
|
|
|
|
if ((master < 0) || (master >= priv->masters)){
|
|
DBG("Wrong master id.\n");
|
|
return GRIOMMU_ERR_EINVAL;
|
|
}
|
|
|
|
if ((group < 0) || (group >= priv->groups)){
|
|
DBG("Wrong group id.\n");
|
|
return GRIOMMU_ERR_EINVAL;
|
|
}
|
|
|
|
griommu_reg_master_set(master,
|
|
((options & GRIOMMU_OPTIONS_BUS1)? MASTER_BS_BUS1: MASTER_BS_BUS0)|
|
|
((group << MASTER_GROUP_BIT) & MASTER_GROUP)
|
|
);
|
|
|
|
DBG("IOMMU master setup: master %d, traffic routed %s, group %d\n",
|
|
master,
|
|
(options & GRIOMMU_OPTIONS_BUS1) ?
|
|
"to Secondary bus":"to Primary bus",
|
|
group);
|
|
|
|
return GRIOMMU_ERR_OK;
|
|
}
|
|
|
|
|
|
/* Get IOMMU master info:
|
|
*/
|
|
int griommu_master_info(int master, uint32_t * info)
|
|
{
|
|
struct griommu_priv * priv = griommupriv;
|
|
|
|
if (priv == NULL){
|
|
DBG("GRIOMMU not initialized.\n");
|
|
return GRIOMMU_ERR_NOINIT;
|
|
}
|
|
|
|
if ((master < 0) || (master >= priv->masters)){
|
|
DBG("Wrong master id.\n");
|
|
return GRIOMMU_ERR_EINVAL;
|
|
}
|
|
|
|
if (info == NULL){
|
|
DBG("Wrong pointer.\n");
|
|
return GRIOMMU_ERR_EINVAL;
|
|
}
|
|
|
|
/* Get master */
|
|
*info = griommu_reg_master(master);
|
|
|
|
return GRIOMMU_ERR_OK;
|
|
}
|
|
|
|
/* Find IOMMU master:
|
|
*/
|
|
int griommu_master_find(int vendor, int device, int instance)
|
|
{
|
|
struct griommu_priv * priv = griommupriv;
|
|
int i, gotvendor, gotdevice;
|
|
unsigned int master;
|
|
int found;
|
|
|
|
if (priv == NULL){
|
|
DBG("GRIOMMU not initialized.\n");
|
|
return GRIOMMU_ERR_NOINIT;
|
|
}
|
|
|
|
/* Find which master */
|
|
found=0;
|
|
for (i=0; i< priv->masters; i++){
|
|
master = griommu_reg_master(i);
|
|
gotvendor = (master & MASTER_VENDOR) >> MASTER_VENDOR_BIT;
|
|
gotdevice = (master & MASTER_DEVICE) >> MASTER_DEVICE_BIT;
|
|
if ((gotvendor == vendor) && (gotdevice == device)){
|
|
if(found == instance){
|
|
DBG("Found master %d: VENDOR=%s(0x%02x), DEVICE=%s(0x%03x), "
|
|
"Instance=%d\n",
|
|
i,
|
|
ambapp_vendor_id2str(vendor), vendor,
|
|
ambapp_device_id2str(vendor,device), device, instance
|
|
);
|
|
return i;
|
|
}
|
|
found++;
|
|
}
|
|
}
|
|
|
|
DBG("Master not found: VENDOR=%s(0x%02x), DEVICE=%s(0x%03x), "
|
|
"Instance=%d\n",
|
|
ambapp_vendor_id2str(vendor), vendor,
|
|
ambapp_device_id2str(vendor,device), device, instance
|
|
);
|
|
return GRIOMMU_ERR_NOTFOUND;
|
|
}
|
|
|
|
/* Setup IOMMU:
|
|
*/
|
|
int griommu_setup(int options)
|
|
{
|
|
struct griommu_priv * priv = griommupriv;
|
|
unsigned int ctrl;
|
|
|
|
if (priv == NULL){
|
|
DBG("GRIOMMU not initialized.\n");
|
|
return GRIOMMU_ERR_NOINIT;
|
|
}
|
|
|
|
/* Check Cache */
|
|
if (options & GRIOMMU_OPTIONS_CACHE_ENABLE) {
|
|
if (priv->apv_cache){
|
|
/* Flush cache */
|
|
griommu_reg_flush_set(FLUSH_F);
|
|
priv->cache_enabled = 1;
|
|
}else{
|
|
DBG("GRIOMMU APV cache not supported.\n");
|
|
return GRIOMMU_ERR_IMPLEMENTED;
|
|
}
|
|
}else{
|
|
priv->cache_enabled = 0;
|
|
}
|
|
|
|
/* Check group addressing */
|
|
if (options & GRIOMMU_OPTIONS_GROUPADDRESSING_ENABLE){
|
|
if (priv->apv_cache_addr){
|
|
priv->group_addressing = 1;
|
|
}else{
|
|
DBG("GRIOMMU APV cache group addressing not supported.\n");
|
|
return GRIOMMU_ERR_IMPLEMENTED;
|
|
}
|
|
}else{
|
|
priv->group_addressing = 0;
|
|
}
|
|
|
|
/* Check pagesize */
|
|
if ((options & CTRL_PGSZ) != GRIOMMU_OPTIONS_PAGESIZE_4KIB){
|
|
if (priv->conf_pagesize == 0){
|
|
DBG("GRIOMMU Configurable pagesize not supported.\n");
|
|
return GRIOMMU_ERR_IMPLEMENTED;
|
|
}
|
|
}
|
|
|
|
/* Get CTRL IOMMU */
|
|
ctrl = griommu_reg_ctrl();
|
|
|
|
/* Clear used fields */
|
|
ctrl &= ~(CTRL_CE | CTRL_GS | CTRL_PGSZ | CTRL_LB |
|
|
CTRL_DP | CTRL_AU | CTRL_WP);
|
|
|
|
/* Clear not used fields */
|
|
options &= (CTRL_CE | CTRL_GS | CTRL_PGSZ | CTRL_LB |
|
|
CTRL_DP | CTRL_AU | CTRL_WP);
|
|
|
|
/* Set new values */
|
|
ctrl |= options;
|
|
|
|
/* Set CTRL IOMMU */
|
|
griommu_reg_ctrl_set(ctrl);
|
|
|
|
DBG("IOMMU setup: prefetching %s, cache %s, groupaddr %s, "
|
|
"lookup bus %s, ahb update %s,\nwprot only %s, pagesize %d KiB\n",
|
|
((options & GRIOMMU_OPTIONS_PREFETCH_DISABLE)?
|
|
"disabled":"enabled"),
|
|
((options & GRIOMMU_OPTIONS_CACHE_ENABLE)? "enabled":"disabled"),
|
|
((options & GRIOMMU_OPTIONS_GROUPADDRESSING_ENABLE)?
|
|
"enabled":"disabled"),
|
|
((options & GRIOMMU_OPTIONS_LOOKUPBUS_BUS1)? "bus1":"bus0"),
|
|
((options & GRIOMMU_OPTIONS_AHBUPDATE_ENABLE)?
|
|
"enabled":"disabled"),
|
|
((options & GRIOMMU_OPTIONS_WPROTONLY_ENABLE)?
|
|
"enabled":"disabled"),
|
|
(4 << ((options & GRIOMMU_OPTIONS_PAGESIZE_512KIB) >> 18))
|
|
);
|
|
|
|
return GRIOMMU_ERR_OK;
|
|
}
|
|
|
|
/* Status IOMMU:
|
|
*/
|
|
int griommu_status(void)
|
|
{
|
|
struct griommu_priv * priv = griommupriv;
|
|
unsigned int ctrl;
|
|
|
|
if (priv == NULL){
|
|
DBG("GRIOMMU not initialized.\n");
|
|
return GRIOMMU_ERR_NOINIT;
|
|
}
|
|
|
|
/* Get CTRL IOMMU */
|
|
ctrl = griommu_reg_ctrl();
|
|
|
|
DBG("IOMMU status: prefetching %s, cache %s, groupaddr %s, "
|
|
"lookup bus %s, ahb update %s,\nwprot only %s, pagesize %d KiB\n",
|
|
((ctrl & CTRL_DP)? "disabled":"enabled"),
|
|
((ctrl & CTRL_CE)? "enabled":"disabled"),
|
|
((ctrl & CTRL_GS)? "enabled":"disabled"),
|
|
((ctrl & CTRL_LB)? "bus1":"bus0"),
|
|
((ctrl & CTRL_AU)? "enabled":"disabled"),
|
|
((ctrl & CTRL_WP)? "enabled":"disabled"),
|
|
(4 << ((ctrl & CTRL_PGSZ) >> CTRL_PGSZ_BIT))
|
|
);
|
|
|
|
return ctrl;
|
|
}
|
|
|
|
int griommu_isr_register(griommu_isr_t isr, void * arg, int options)
|
|
{
|
|
struct griommu_priv *priv = griommupriv;
|
|
unsigned int mask;
|
|
|
|
if (priv == NULL){
|
|
DBG("GRIOMMU not initialized.\n");
|
|
return GRIOMMU_ERR_NOINIT;
|
|
}
|
|
|
|
if (isr == NULL){
|
|
DBG("GRIOMMU wrong isr.\n");
|
|
return GRIOMMU_ERR_EINVAL;
|
|
}
|
|
|
|
/* Get mask */
|
|
mask = 0 |
|
|
((options & GRIOMMU_INTERRUPT_PARITY_ERROR)? IMASK_PEI:0) |
|
|
((options & GRIOMMU_INTERRUPT_FLUSH_COMPLETED)? IMASK_FCI:0) |
|
|
((options & GRIOMMU_INTERRUPT_FLUSH_START)? IMASK_FLI:0) |
|
|
((options & GRIOMMU_INTERRUPT_ACCESS_DENIED)? IMASK_ADI:0) |
|
|
((options & GRIOMMU_INTERRUPT_TRANSLATION_ERROR)? IMASK_TEI:0);
|
|
|
|
/* Clear previous interrupts and mask them*/
|
|
griommu_reg_status_clear(STS_ALL);
|
|
griommu_reg_imask_set(0);
|
|
|
|
/* First time registering an ISR */
|
|
if (priv->isr == NULL){
|
|
/* Install and Enable GRIOMMU interrupt handler */
|
|
drvmgr_interrupt_register(priv->dev, 0, priv->devname, griommu_isr,
|
|
priv);
|
|
}
|
|
|
|
/* Install user ISR */
|
|
priv->isr=isr;
|
|
priv->isr_arg=arg;
|
|
|
|
/* Now it is safe to unmask interrupts */
|
|
griommu_reg_imask_set(mask);
|
|
|
|
return GRIOMMU_ERR_OK;
|
|
}
|
|
|
|
int griommu_isr_unregister(void)
|
|
{
|
|
struct griommu_priv *priv = griommupriv;
|
|
|
|
if (priv == NULL){
|
|
DBG("GRIOMMU not initialized.\n");
|
|
return GRIOMMU_ERR_NOINIT;
|
|
}
|
|
|
|
if (priv->isr == NULL){
|
|
DBG("GRIOMMU wrong isr.\n");
|
|
return GRIOMMU_ERR_EINVAL;
|
|
}
|
|
|
|
/* Clear previous interrupts and mask them*/
|
|
griommu_reg_status_clear(STS_ALL);
|
|
griommu_reg_imask_set(0);
|
|
|
|
/* Uninstall and disable GRIOMMU interrupt handler */
|
|
drvmgr_interrupt_unregister(priv->dev, 0, griommu_isr, priv);
|
|
|
|
/* Uninstall user ISR */
|
|
priv->isr=NULL;
|
|
priv->isr_arg=NULL;
|
|
|
|
return GRIOMMU_ERR_OK;
|
|
}
|
|
|
|
int griommu_interrupt_unmask(int options)
|
|
{
|
|
struct griommu_priv *priv = griommupriv;
|
|
unsigned int mask, irq;
|
|
|
|
if (priv == NULL){
|
|
DBG("GRIOMMU not initialized.\n");
|
|
return GRIOMMU_ERR_NOINIT;
|
|
}
|
|
|
|
if (priv->isr == NULL){
|
|
DBG("GRIOMMU wrong isr.\n");
|
|
return GRIOMMU_ERR_EINVAL;
|
|
}
|
|
|
|
/* Unmask interrupts in GRIOMMU */
|
|
mask = 0 |
|
|
((options & GRIOMMU_INTERRUPT_PARITY_ERROR)? IMASK_PEI:0) |
|
|
((options & GRIOMMU_INTERRUPT_FLUSH_COMPLETED)? IMASK_FCI:0) |
|
|
((options & GRIOMMU_INTERRUPT_FLUSH_START)? IMASK_FLI:0) |
|
|
((options & GRIOMMU_INTERRUPT_ACCESS_DENIED)? IMASK_ADI:0) |
|
|
((options & GRIOMMU_INTERRUPT_TRANSLATION_ERROR)? IMASK_TEI:0);
|
|
|
|
/* Clear previous interrupts*/
|
|
griommu_reg_status_clear(STS_ALL);
|
|
|
|
/* Get previous mask */
|
|
irq = griommu_reg_imask() & IMASK_ALL;
|
|
|
|
/* Set new mask */
|
|
griommu_reg_imask_set(irq | mask);
|
|
|
|
return GRIOMMU_ERR_OK;
|
|
}
|
|
|
|
int griommu_interrupt_mask(int options)
|
|
{
|
|
struct griommu_priv *priv = griommupriv;
|
|
unsigned int mask, irq;
|
|
|
|
if (priv == NULL){
|
|
DBG("GRIOMMU not initialized.\n");
|
|
return GRIOMMU_ERR_NOINIT;
|
|
}
|
|
|
|
if (priv->isr == NULL){
|
|
DBG("GRIOMMU wrong isr.\n");
|
|
return GRIOMMU_ERR_EINVAL;
|
|
}
|
|
|
|
/* Mask interrupts in GRIOMMU */
|
|
mask = 0 |
|
|
((options & GRIOMMU_INTERRUPT_PARITY_ERROR)? IMASK_PEI:0) |
|
|
((options & GRIOMMU_INTERRUPT_FLUSH_COMPLETED)? IMASK_FCI:0) |
|
|
((options & GRIOMMU_INTERRUPT_FLUSH_START)? IMASK_FLI:0) |
|
|
((options & GRIOMMU_INTERRUPT_ACCESS_DENIED)? IMASK_ADI:0) |
|
|
((options & GRIOMMU_INTERRUPT_TRANSLATION_ERROR)? IMASK_TEI:0);
|
|
|
|
/* Clear previous interrupts*/
|
|
griommu_reg_status_clear(STS_ALL);
|
|
|
|
/* Get previous mask */
|
|
irq = griommu_reg_imask() & IMASK_ALL;
|
|
|
|
/* Set new mask */
|
|
griommu_reg_imask_set(irq & ~(mask));
|
|
|
|
return GRIOMMU_ERR_OK;
|
|
}
|
|
|
|
int griommu_error_status(uint32_t * access)
|
|
{
|
|
struct griommu_priv *priv = griommupriv;
|
|
int status;
|
|
|
|
if (priv == NULL){
|
|
DBG("GRIOMMU not initialized.\n");
|
|
return GRIOMMU_ERR_NOINIT;
|
|
}
|
|
|
|
/* Get status mask */
|
|
status = griommu_reg_status();
|
|
|
|
if (status != 0){
|
|
/* Update pointed value */
|
|
if (access != NULL){
|
|
*access = griommu_reg_ahbfas();
|
|
}
|
|
/* Clear errors */
|
|
griommu_reg_status_clear(status);
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/* Print IOMMU masters
|
|
* DEBUG function
|
|
*/
|
|
int griommu_print(void)
|
|
{
|
|
#ifdef DEBUG
|
|
struct griommu_priv * priv = griommupriv;
|
|
unsigned int ctrl;
|
|
|
|
if (priv == NULL){
|
|
DBG("GRIOMMU not initialized.\n");
|
|
return GRIOMMU_ERR_NOINIT;
|
|
}
|
|
|
|
/* Print IOMMU status */
|
|
ctrl = griommu_reg_ctrl();
|
|
|
|
printf("IOMMU status: prefetching %s, lookup bus %s, ahb update %s,\n"
|
|
"wprot only %s, pagesize %d KiB\n",
|
|
((ctrl & CTRL_DP)? "disabled":"enabled"),
|
|
((ctrl & CTRL_LB)? "bus1":"bus0"),
|
|
((ctrl & CTRL_AU)? "enabled":"disabled"),
|
|
((ctrl & CTRL_WP)? "enabled":"disabled"),
|
|
(4 << ((ctrl & CTRL_PGSZ) >> CTRL_PGSZ_BIT))
|
|
);
|
|
|
|
/* Print each master configuration */
|
|
int i, vendor, device, routing;
|
|
unsigned int master;
|
|
for (i=0; i < priv->masters; i++){
|
|
master = griommu_reg_master(i);
|
|
vendor = (master & MASTER_VENDOR) >> MASTER_VENDOR_BIT;
|
|
device = (master & MASTER_DEVICE) >> MASTER_DEVICE_BIT;
|
|
routing = (master & MASTER_BS);
|
|
printf("IOMMU master %d: VENDOR=%s(0x%02x), DEVICE=%s(0x%03x), "
|
|
"BS=%s\n",
|
|
i,
|
|
ambapp_vendor_id2str(vendor), vendor,
|
|
ambapp_device_id2str(vendor,device), device,
|
|
(routing == MASTER_BS_BUS0? "Primary bus" : "Secondary bus")
|
|
);
|
|
}
|
|
#endif
|
|
return GRIOMMU_ERR_OK;
|
|
}
|
|
|
|
void * griommu_apv_new(void)
|
|
{
|
|
struct griommu_priv * priv = griommupriv;
|
|
|
|
if (priv == NULL){
|
|
DBG("GRIOMMU not initialized.\n");
|
|
return NULL;
|
|
}
|
|
|
|
/* Allocate APV */
|
|
unsigned int * orig_ptr = grlib_malloc(
|
|
(GRIOMMU_APV_SIZE/priv->pagesize) + GRIOMMU_APV_ALIGN);
|
|
if (orig_ptr == NULL) return NULL;
|
|
|
|
/* Get the aligned pointer */
|
|
unsigned int aligned_ptr = (
|
|
((unsigned int) orig_ptr + GRIOMMU_APV_ALIGN) &
|
|
~(GRIOMMU_APV_ALIGN - 1));
|
|
|
|
/* Save the original pointer before the aligned pointer */
|
|
unsigned int ** tmp_ptr =
|
|
(unsigned int **) (aligned_ptr - sizeof(orig_ptr));
|
|
*tmp_ptr= orig_ptr;
|
|
|
|
/* Return aligned pointer */
|
|
return (void *) aligned_ptr;
|
|
}
|
|
|
|
void griommu_apv_delete(void * apv)
|
|
{
|
|
/* Recover orignal pointer placed just before the aligned pointer */
|
|
unsigned int * orig_ptr;
|
|
unsigned int ** tmp_ptr = (unsigned int **) (apv - sizeof(orig_ptr));
|
|
orig_ptr = *tmp_ptr;
|
|
|
|
/* Deallocate memory */
|
|
free(orig_ptr);
|
|
}
|
|
|
|
int griommu_enable(int mode)
|
|
{
|
|
struct griommu_priv * priv = griommupriv;
|
|
unsigned int ctrl;
|
|
|
|
if (priv == NULL){
|
|
DBG("GRIOMMU not initialized.\n");
|
|
return GRIOMMU_ERR_NOINIT;
|
|
}
|
|
|
|
switch (mode){
|
|
case GRIOMMU_MODE_IOMMU:
|
|
default:
|
|
DBG("IOMMU mode not implemented in driver.\n");
|
|
return GRIOMMU_ERR_EINVAL;
|
|
break;
|
|
case GRIOMMU_MODE_GROUPAPV:
|
|
if (priv->apv == 0){
|
|
DBG("IOMMU APV not supported.\n");
|
|
return GRIOMMU_ERR_IMPLEMENTED;
|
|
}
|
|
/* Enable IOMMU */
|
|
ctrl = (griommu_reg_ctrl() & ~(CTRL_PM));
|
|
griommu_reg_ctrl_set(ctrl | CTRL_PM_APV | CTRL_EN);
|
|
|
|
/* Wait until change has effect */
|
|
while((griommu_reg_ctrl() & CTRL_EN)==0){};
|
|
|
|
DBG("IOMMU enabled.\n");
|
|
return GRIOMMU_ERR_OK;
|
|
break;
|
|
}
|
|
return GRIOMMU_ERR_OK;
|
|
}
|
|
|
|
int griommu_disable(void)
|
|
{
|
|
struct griommu_priv * priv = griommupriv;
|
|
unsigned int ctrl;
|
|
|
|
if (priv == NULL){
|
|
DBG("GRIOMMU not initialized.\n");
|
|
return GRIOMMU_ERR_NOINIT;
|
|
}
|
|
|
|
/* Disable IOMMU */
|
|
ctrl = (griommu_reg_ctrl() & ~(CTRL_EN));
|
|
griommu_reg_ctrl_set(ctrl);
|
|
|
|
/* Wait until change has effect */
|
|
while(griommu_reg_ctrl() & CTRL_EN){};
|
|
|
|
return GRIOMMU_ERR_OK;
|
|
}
|
|
|
|
int griommu_group_setup(int group, void * apv, int options)
|
|
{
|
|
struct griommu_priv * priv = griommupriv;
|
|
|
|
if (priv == NULL){
|
|
DBG("GRIOMMU not initialized.\n");
|
|
return GRIOMMU_ERR_NOINIT;
|
|
}
|
|
|
|
if ((group < 0) || (group >= priv->groups)){
|
|
DBG("Wrong group id.\n");
|
|
return GRIOMMU_ERR_EINVAL;
|
|
}
|
|
|
|
if ((options < 0) || (options > GRIOMMU_OPTIONS_GROUP_PASSTHROUGH)){
|
|
DBG("Wrong options.\n");
|
|
return GRIOMMU_ERR_EINVAL;
|
|
}
|
|
|
|
if (options == GRIOMMU_OPTIONS_GROUP_DISABLE){
|
|
if ((unsigned int) apv & (GRIOMMU_APV_ALIGN -1)){
|
|
DBG("Wrong pointer.\n");
|
|
return GRIOMMU_ERR_EINVAL;
|
|
}
|
|
|
|
/* Disable GROUP */
|
|
griommu_reg_group_set(group, (((unsigned int) apv) & GRP_BASE) | 0);
|
|
DBG("GROUP[%d] DISABLED.\n", group);
|
|
return GRIOMMU_ERR_OK;
|
|
}else if (options == GRIOMMU_OPTIONS_GROUP_PASSTHROUGH){
|
|
if ((unsigned int) apv & (GRIOMMU_APV_ALIGN -1)){
|
|
DBG("Wrong pointer.\n");
|
|
return GRIOMMU_ERR_EINVAL;
|
|
}
|
|
|
|
/* Group in passthrough */
|
|
griommu_reg_group_set(group,
|
|
(((unsigned int) apv) & GRP_BASE) | GRP_P | GRP_AG);
|
|
DBG("GROUP[%d] set to PASSTHROUGH.\n", group);
|
|
return GRIOMMU_ERR_OK;
|
|
}else{
|
|
if (priv->apv == 0){
|
|
DBG("IOMMU APV not supported.\n");
|
|
return GRIOMMU_ERR_IMPLEMENTED;
|
|
}
|
|
|
|
if ((apv == NULL) || ((unsigned int) apv & (GRIOMMU_APV_ALIGN -1))){
|
|
DBG("Wrong pointer.\n");
|
|
return GRIOMMU_ERR_EINVAL;
|
|
}
|
|
|
|
/* Set up base and enable */
|
|
griommu_reg_group_set(group,
|
|
(((unsigned int) apv) & GRP_BASE) | GRP_AG);
|
|
DBG("GROUP[%d] set to APV (0x%08x).\n", group, (unsigned int) apv);
|
|
return GRIOMMU_ERR_OK;
|
|
}
|
|
}
|
|
|
|
int griommu_group_apv_init(int group, int options)
|
|
{
|
|
struct griommu_priv * priv = griommupriv;
|
|
void * apv;
|
|
int val;
|
|
int ret;
|
|
size_t len;
|
|
|
|
/* Flush APV cache if needed.
|
|
* This function checks for priv and group being valid.*/
|
|
ret = griommu_group_apv_flush(group);
|
|
if (ret < 0){
|
|
return ret;
|
|
}
|
|
|
|
/* Get APV group */
|
|
apv = (void *) (griommu_reg_group(group) & GRP_BASE);
|
|
|
|
if (apv == NULL){
|
|
DBG("Wrong pointer.\n");
|
|
return GRIOMMU_ERR_NOTFOUND;
|
|
}
|
|
|
|
/* Get init value (is a char) */
|
|
if (options == GRIOMMU_OPTIONS_APV_ALLOW){
|
|
val = 0x00;
|
|
}else{
|
|
val = 0xff;
|
|
}
|
|
|
|
/* Get APV length */
|
|
len = GRIOMMU_APV_SIZE/priv->pagesize;
|
|
|
|
/* Initialize structure */
|
|
memset(apv, val, len);
|
|
|
|
return GRIOMMU_ERR_OK;
|
|
}
|
|
|
|
int griommu_group_apv_page_set(int group, int index, int size, int options)
|
|
{
|
|
void * apv;
|
|
unsigned int val;
|
|
int ret;
|
|
|
|
/* Flush APV cache if needed.
|
|
* This function checks for priv and group being valid.*/
|
|
ret = griommu_group_apv_flush(group);
|
|
if (ret < 0){
|
|
return ret;
|
|
}
|
|
|
|
/* Get APV group */
|
|
apv = (void *) (griommu_reg_group(group) & GRP_BASE);
|
|
|
|
if (apv == NULL){
|
|
DBG("Wrong pointer.\n");
|
|
return GRIOMMU_ERR_NOTFOUND;
|
|
}
|
|
|
|
/* Get init value */
|
|
if (options == GRIOMMU_OPTIONS_APV_ALLOW){
|
|
val = 0x0;
|
|
}else{
|
|
val = 0xffffffff;
|
|
}
|
|
|
|
return griommu_apv_set(apv, index, size, val);
|
|
}
|
|
|
|
int griommu_group_apv_address_set(int group, uint32_t addr, int size,
|
|
int options)
|
|
{
|
|
struct griommu_priv * priv = griommupriv;
|
|
void * apv;
|
|
unsigned int val;
|
|
int ret;
|
|
int startpage;
|
|
int endpage;
|
|
int npages;
|
|
|
|
/* Flush APV cache if needed.
|
|
* This function checks for priv and group being valid.*/
|
|
ret = griommu_group_apv_flush(group);
|
|
if (ret < 0){
|
|
return ret;
|
|
}
|
|
|
|
/* Get APV group */
|
|
apv = (void *) (griommu_reg_group(group) & GRP_BASE);
|
|
|
|
if (apv == NULL){
|
|
DBG("Wrong pointer.\n");
|
|
return GRIOMMU_ERR_NOTFOUND;
|
|
}
|
|
|
|
/* Get init value */
|
|
if (options == GRIOMMU_OPTIONS_APV_ALLOW){
|
|
val = 0x0;
|
|
}else{
|
|
val = 0xffffffff;
|
|
}
|
|
|
|
/* Get start page */
|
|
startpage = (addr / priv->pagesize);
|
|
|
|
/* Get end page */
|
|
endpage = ((addr + size)/ priv->pagesize);
|
|
|
|
/* Get number of pages */
|
|
npages = endpage - startpage + 1;
|
|
|
|
return griommu_apv_set(apv, startpage, npages, val);
|
|
}
|
|
|
|
int griommu_apv_init(void * apv, int options)
|
|
{
|
|
struct griommu_priv * priv = griommupriv;
|
|
int val;
|
|
size_t len;
|
|
|
|
if (priv == NULL){
|
|
DBG("GRIOMMU not initialized.\n");
|
|
return GRIOMMU_ERR_NOINIT;
|
|
}
|
|
|
|
if ((apv == NULL) || ((unsigned int) apv & (GRIOMMU_APV_ALIGN -1))){
|
|
DBG("Wrong pointer.\n");
|
|
return GRIOMMU_ERR_EINVAL;
|
|
}
|
|
|
|
/* Get init value (is a char) */
|
|
if (options == GRIOMMU_OPTIONS_APV_ALLOW){
|
|
val = 0x00;
|
|
}else{
|
|
val = 0xff;
|
|
}
|
|
|
|
/* Get APV length */
|
|
len = GRIOMMU_APV_SIZE/priv->pagesize;
|
|
|
|
/* Initialize structure */
|
|
memset(apv, val, len);
|
|
|
|
return GRIOMMU_ERR_OK;
|
|
}
|
|
|
|
int griommu_apv_page_set(void * apv, int index, int size, int options)
|
|
{
|
|
struct griommu_priv * priv = griommupriv;
|
|
unsigned int val;
|
|
|
|
if (priv == NULL){
|
|
DBG("GRIOMMU not initialized.\n");
|
|
return GRIOMMU_ERR_NOINIT;
|
|
}
|
|
|
|
if ((apv == NULL) || ((unsigned int) apv & (GRIOMMU_APV_ALIGN -1))){
|
|
DBG("Wrong pointer.\n");
|
|
return GRIOMMU_ERR_EINVAL;
|
|
}
|
|
|
|
/* Get init value */
|
|
if (options == GRIOMMU_OPTIONS_APV_ALLOW){
|
|
val = 0x0;
|
|
}else{
|
|
val = 0xffffffff;
|
|
}
|
|
|
|
return griommu_apv_set(apv, index, size, val);
|
|
}
|
|
|
|
int griommu_apv_address_set(void * apv, uint32_t addr, int size, int options)
|
|
{
|
|
struct griommu_priv * priv = griommupriv;
|
|
unsigned int val;
|
|
int startpage;
|
|
int endpage;
|
|
int npages;
|
|
|
|
if (priv == NULL){
|
|
DBG("GRIOMMU not initialized.\n");
|
|
return GRIOMMU_ERR_NOINIT;
|
|
}
|
|
|
|
if ((apv == NULL) || ((unsigned int) apv & (GRIOMMU_APV_ALIGN -1))){
|
|
DBG("Wrong pointer.\n");
|
|
return GRIOMMU_ERR_EINVAL;
|
|
}
|
|
|
|
/* Get init value */
|
|
if (options == GRIOMMU_OPTIONS_APV_ALLOW){
|
|
val = 0x0;
|
|
}else{
|
|
val = 0xffffffff;
|
|
}
|
|
|
|
/* Get start page */
|
|
startpage = (addr / priv->pagesize);
|
|
|
|
/* Get end page */
|
|
endpage = ((addr + size)/ priv->pagesize);
|
|
|
|
/* Get number of pages */
|
|
npages = endpage - startpage + 1;
|
|
|
|
return griommu_apv_set(apv, startpage, npages, val);
|
|
}
|
|
|
|
int griommu_group_info(int group, uint32_t * info)
|
|
{
|
|
struct griommu_priv * priv = griommupriv;
|
|
|
|
if (priv == NULL){
|
|
DBG("GRIOMMU not initialized.\n");
|
|
return GRIOMMU_ERR_NOINIT;
|
|
}
|
|
|
|
if ((group < 0) || (group >= priv->groups)){
|
|
DBG("Wrong group id.\n");
|
|
return GRIOMMU_ERR_EINVAL;
|
|
}
|
|
|
|
if (info == NULL){
|
|
DBG("Wrong pointer.\n");
|
|
return GRIOMMU_ERR_EINVAL;
|
|
}
|
|
|
|
/* Get group */
|
|
*info = griommu_reg_group(group);
|
|
|
|
return GRIOMMU_ERR_OK;
|
|
}
|
|
|
|
/* Flush APV cache group:
|
|
*/
|
|
int griommu_group_apv_flush(int group)
|
|
{
|
|
struct griommu_priv * priv = griommupriv;
|
|
|
|
if (priv == NULL){
|
|
DBG("GRIOMMU not initialized.\n");
|
|
return GRIOMMU_ERR_NOINIT;
|
|
}
|
|
|
|
if ((group < 0) || (group >= priv->groups)){
|
|
DBG("Wrong group id.\n");
|
|
return GRIOMMU_ERR_EINVAL;
|
|
}
|
|
|
|
/* Flush cache */
|
|
if (priv->cache_enabled){
|
|
if (priv->group_addressing){
|
|
griommu_reg_flush_set(((group << FLUSH_FGRP_BIT) & FLUSH_FGRP) |
|
|
FLUSH_GF | FLUSH_F);
|
|
}else{
|
|
griommu_reg_flush_set(FLUSH_F);
|
|
}
|
|
DBG("GRIOMMU APV cache flushed.\n");
|
|
}
|
|
|
|
return GRIOMMU_ERR_OK;
|
|
}
|
|
|
|
/* Flush APV cache:
|
|
*/
|
|
int griommu_apv_flush(void)
|
|
{
|
|
struct griommu_priv * priv = griommupriv;
|
|
|
|
if (priv == NULL){
|
|
DBG("GRIOMMU not initialized.\n");
|
|
return GRIOMMU_ERR_NOINIT;
|
|
}
|
|
|
|
/* Flush cache */
|
|
if (priv->cache_enabled){
|
|
griommu_reg_flush_set(FLUSH_F);
|
|
DBG("GRIOMMU APV cache flushed.\n");
|
|
}
|
|
|
|
return GRIOMMU_ERR_OK;
|
|
}
|
|
|